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A-8
Cl)
0
z
0
0
w
Cl)
36
34
32
30
0
,,,,.,--
z >-
Cl)
28
<( <(
w
z
...I
~
_, w
(.!)
wO
(.!)
...I
a::
<( <(
w
I- I-
CD
~o~
>- ...... z
<(~
...I
w
0
w
(.!)
<(
a::
26
24
22
~
20
<(
18
16
0
10
20
TYPICAL CIRCUIT DELAY OF NANO GATES
SYSTEM OPERATING AMBIENT: +55°C
8 LOADS
I ACTIVE
40
50
Vee= +6 VOLTS
5 LOADS
3 LOADS
I ACTIVE
I ACTIVE
60
70
80
541
BACK PLANE WIRING CAPACITANCE
(pf)
Figure A-2.
Typical NAND Gate Circuit Delays (Sheet 3 of 3)
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