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Instruction Execution Sequence
Program instruction processing (refer to Figure 2-8) requires from one to three
types of machine phases.
These phases are called F, A, and I.
Instructions are composed
of an integral number of phases, where each phase sets up the following one, depending on
the instruction being performed.
Every instruction has an F phase.
This phase fetches the instruction to be performed
and if the instruction word calls for indirect add res sing, the F phase sets up an I phase.
The I phase uses the address generated by the F-phase to fetch a new address and
if the new address calls another indirect address, an additional I phase is set up.
All memory reference instructions except JMP have at least one A phase.
It is during
an A phase that operands are fetched or stored and/or operated upon.
When multiple or ex-
tended A phases are necessary, the shift counter is used.
The operand address used by the A phase is called the "effective operand address"
(EA).
It is established in the previous F or I phase.
The last A phase sets up the F
phase for the next instruction.
All instructions are composed of one of the nine phase sequences shown below:
F ---.. I
I .
F ---.. A-. F
F -. I -A -.F
F - I -. I .
-
I ---.. A -F
F -A -A.
-. A -. F
F -. I -.A -A.
.-A
-
F
F - I - I .
-
I
-A
-~A
-A -F
The use of optional I/O devices can cause "breaks" and "interrupts" in the normal
execution of a program in progress.
A break is defined as an operatior which interjects
a function without altering the P-register.
An interrupt is defined as an operation which
interrupts the normal sequencing of instructions being performed by altering the P-register.
The computer breaks are RTC, MI, DMC, and DMA.
RTC, MI, and DMC breaks
can only occur when the CPU has completed an instruction.
DMA can cause a break with-
out waiting for the end of an instruction.
SI and PI can interrupt only when the CPU is in
the "permit interrupt" status.
ML and PF! can interrupt regardless of the "permit inter-
rupt" status.
Programs stored in memory can be executed at normal operating speed or may be
examined in detail by executing one instruction at a time.
Setting front panel controls for
single instruction operation permits the first instruction, and every instruction thereafter,
to be examined with front panel controls and indicators.
Depressing the START button
initiates the analysis.
Thereafter, each time the START button is activated, the previously
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