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SELECTION PAC, MODEL CM-006/106
GENERAL DESCRIPTION
The Selection PAC, Model CM-006/106 (Figures A-66 and A-67), contains eight
transformer driven transistor switches connected as four (read-write) switch pairs.
The
CM-006 utilizes two F-03 microcircuit power amplifiers with decoding inputs for two address
bits and a decoding enable input.
An F-06 microcircuit multi-emitter gate provides timing
(read-write) and matrix enable inputs.
The PAC may be used as an 'X
1
or 'Y
1
selection
switch or sink.
The CM-106 PAC does not contain the F-03 integrated circuits for address input
decoding but is otherwise similar to the CM-006.
CIRCUIT FUNCTION
Two binary address inputs are decoded to select one of the four F-03 integrated
circuits.
When the decoding enable input is passive, the output of the selected F-03 circuit
will be at Ov.
The multi-emitter circuit is turned on when the timing and matrix enable
inputs are at +6v.
Current flows through the primary of the transformer which is connected
to the enabled F-03 and F-06 circuits.
The output transistor is turned on by the secondary
of the selected transformer.
The basic selection scheme of the CM-006 can be expanded by jumpering pins 3,
5, 9, and 24 to the corresponding pins on the CM-106.
Decoding of the two address inputs
\Vill then be common to both P . . . fl.Cs.
F-03 and F-06 circuit inputs.
SPECIFICATIONS
Input Loading
Timing (read-write) inputs:
Matrix enable inputs:
Address inputs:
Decoding enable inputs:
l unit load
2 unit loads
3 unit loads
4 unit loads
Outputs Characteristics
Turn-on delay (1. 5v of timing input to
10% of output current):
Turn-off delay ( 1. 5v of decoding enable
input to 90% of output
current):
Rise time (10%-90%): 80 ns (max)
Fall time (90%-10%): 80 ns (max)
Current:
Voltage:
Pulse width:
Duty cycle:
425 ma (max)
30v (max)
400 ns (max)
45% (max)
40 ns (max)
90 ns (max)
A-113
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