Memory Cycle Timing; Interface Timing Requirements - Honeywell DDP-416 Instruction Manual

Storage Mode:
Coincident-current magnetic core array (2-1/2 D, 3-wire}
Cycle Time:
Access Time:
O.
96
µsec
0. 48 µsec
Input /Output Levels
Passive: +6 volts
Active:
GND
MEMORY CYCLE TIMING (See Figure 2-24)
For each memory cycle, the CPU must provide the memory with an address, a
start signal and a read or write indication. Once the cycle has been initiated, another can-
not be started until 0. 96 µsec has elapsed.
2-32
CI
(NOTE I)
YXXXX ~,
BANK X-
(NOTE 2)
MDXXX-
MXXXX-
RRCXX+
JliJI
TIME ( nanoHconda)
0
100 200 300 400 500 600 700 800 900 960
3.0
CYCLE INITIATE
- ~--3;~r:--
ADDRESS
=
16-------------------------------->985 ----------------------------------------~
DATA OUT
s200----.
_r.- - -
---READ-RESTOl<E - - - - -
--x
I 3.0
I.I CLEAR-WRITE \..._ - - - - - - -
ALL TIMES MEASURED AT MEMORY MODULE
NOTE I: Cl IS FORMED BY THE LOGICAL AND OF MCSET+ AND MEMCI+.
NOTE 2: THE ADDRESS TRUE ( YXXXX+
l
AND ADDRESS COMPLEMENT ( YXXXX-
l
SHALL REMAIN STABLE
DURING THE INTERVAL FROM
90
NSEC TO
925
NSEC AFTER EACH CYCLE INITIATE.
Figure 2-24. Interface Timing Requirements