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To satisfy timing requirements, the sum logic for stage 1 is extended by a process
analogous to the carry anticipation discussed in the preceding section:
s
l
=
G
1 (G 1
+ H
1 }
E
2
+
(G 1
+
H 1 }
(G
1
+ H
1 }
c
2
+
(G 1
+ H
l } H 1
c
2
where
therefore,
S
l
=
G
1 (G 1
+ H
1 }
C
2
+
(G 1
+
H 1 } H 1
E
2
+
(G 1
+
H 1 }
(G
1
+ H
1 } G 2 . H 2
+
s
1
=
G
l (G 1
+ H
1 }
C
2
+
(G 1
+ Hl }
H 1
C
2
+
(G 1
+
H 1 }
(G
1
+ H
1 } (G 2
+ H
2}
( 3}
This is the function implemented on LBO 101.
Another special case appears on LBD 130, where the extended-sign-bit, D
0
, is created
by combining the carry, C
1
, with extended summand signs, G
1
and H
1
:
But,
C 1
=
G 1
H 1
+
(G 1
+
H 1 ) C 2
when
Hence,
Addition.
This paragraph contains a discussion dealing with the addition of two positive
numbers, a positive and a negative number, and two negative numbers.
These examples
represent the three different combinations encountered in addition.
Arithmetic operations in a two's complement oriented machine are logically easier
to implement because the sign need not be considered.
The following examples show that
in two's complement arithmetic, only binary additions are required regardless of the sign
of the data words.
2-19
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