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becomes +6 volts.
YSWRL+ occurs and turns on 01 (assuming BANKX+X is at +6 volts).
Read current flows from +V, through RZ, 01, CRZ, Yl and 04, to +V.
Because of the
orientation of the core array, only the core on the A half of drive line Y 1 will switch.
The
output of the selected core is sensed and ultimately sets the data register to a ONE.
The address levels and enabling inputs (ENSKltX and ENYSW+X) are the same
during the write portion of the cycle.
When the timing inputs (YSWRH+X and YSKRH+X) are
generated, transistors OZ and 03 are turned on.
This reverses Y - drive current polarity
and write current flows from +V through 03, Yl, CRl, OZ and R3, to -V.
The coincidence
of X- and Y- drive currents results in the generation of a ONE in the selected core.
Write Y - drive current flows only if the data bit is at 0 volt.
If a ZERO is to be
written into the selected core, MXXXX will be at +6 volts and the Y - switch is prevented
from turning on.The selected core receives only an X- write current so it remains in the
ZERO state.
If YlOXX is in the ONE state, read current flows through R3, OZ, CRl, Yl and
03.
Similarly, write current flows through RZ, 01, CRZ, Yl, and 04.
This results in the
selection of a core in the B half of Y 1.
The selection method shown in Figure Z-28
used for X- and Y- selection in 4K and
8K memories.
Y- selection is the same for both memories.
However, 4K memories re-
quire fewer X- selection switches than 8K memories.
TIMING AND CONTROL
The logical functions associated with the control and distribution of memory func -
tions are shown in the logic diagrams.
Timing diagram for the standard memory is shown
in LBD No. l 6Z of Volume III.
Operating Modes
Since the DDP-416 memory does not contain registers, operation in the clear-write
mode is almost identical to that of the read-restore mode.
The exception is that during
clear-write operation, the read-restore command (RRCXX+) is at 0 volt and the sense ampli-
fier strobe is disabled.
When the strobe is disabled, no data can be presented on the data
output lines.
The state of RRCXX+ does not affect internal timing.
Internally Generated Timing
A memory cycle is initiated by the simultaneous assertion of the master clock input
(MCSET+) and memory cycle enable (MEMCI+).
If
the memory is busy, input commands will
not be accepted until the full memory cycle is completed.
The memory is busy if either
MBSYL- or RCYFl- is active.
Simultaneous assertion of MBSYL-, RCYFl-, MEMCI+ and MCSET+ will initiate a
memory cycle.
A flip-flop on the CM-003 µ-PAC will be set, generating a series of pulses.
The timing of these pulses is determined by delay-line jumpers.
The flip-flop is reset by
2-42
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