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Data Storage
The various data storage registers in the central processor are formed with cross-
coupled gates.
With rare exceptions, all data transfers into these registers are perforrned
by clearing all bits of the registers and then setting selected bits of the register to the
desired state.
{The D register is cleared by setting it to all ONEs.)
These two steps are actually carried out in overlapping fashion using the MCRST and
MCSET master clock signals.
Figure 2-22 is a simplified logic diagram of a typical data
transfer depicting the control and timing of these paths.
The numbers in parenthesis denote
the latest times at which various key signals stabilize {measured in nanoseconds from the
end of the previous MCO cycle).
The clearing (MCRST) and setting (MCSET) signals reach
the receiving register simultaneously.
Proper operation is ensured by the earlier termina-
tion of MCRST, combined with the common collector connection of the set gate to the flip-
flop.
(See Figure 2-22.)
Operation Decoding
The output of the F-register is used at the input of two binary-to-octal decoders
(LBD 120)to develop signals for the various Op Codes used in the central processor.
The
F-register is loaded from the M-register during an F-cycle.
With reference to Table 2-2,
note that bit F03 enables only one of the two decoders at a time.
Bits F04, F05, and F06
determine the specific Op Code.
' T ' -
L l -
')
')
.1. ciU.Lt::
t...
-t....
Op Code Decoding
Op Code
F03
F04
F05
F06
IRSOP-
1
0
1
0
JS TOP-
1
0
0
0
}AlC27-A
IOCiRP-
1
1
0
0
{LBD 120)
ANA OP-
0
0
1
1
'
LDAOP-
0
0
1
0
JM POP-
0
0
0
1
OPGOO-
0
0
0
0
SUB OP-
0
1
1
1
>-AlC28-A
{LBD 120)
ADDOP-
0
1
1
0
ERA OP-
0
1
0
1
STAOP-
0
1
0
0
~
2-27
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