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Circuit Delay
(Measured at the +l. Sv level, and averaged over 2 stages)
24 nsec (typ)
30 nsec (max)
The maximum delay specifications stated in the detailed µ.-PAC descriptions are
based on worst-case loading conditions for both turn on and turn off.
Typical delays are
based on one-half maximum rated loading.
Load Resistors in Parallel
When the outputs of two type F-02 NAND gates are tied together, the structure has
a fanout capability of 4 unit loads (two load resistors are in parallel).
When the outputs of
three type F-02 NAND gates are tied together, the structure has a fanout of 1 unit load
(three load resistors are in parallel).
Load Resistors
in Parallel
2
3
Paralleling Outputs with One Load Resistor
Output Drive
Capability
8
4
The maximum number of type F-01 NAND gate collector outputs that can be con-
nected to one load resistor is limited by the maximum tolerable delay.
The average propa-
gation delay increased 3 nsec for each additional collector output that is jumpered through
a connector to a standard output.
TYPE F-03 POWER AMPLIFIER CHARACTERISTICS
The type F-03 power amplifier microcircuit has two 3-input inverter amplifiers
with nodes for input gating expansion.
(See Figure A- 7.) The power amplifier circuit is
logically equivalent to the NAND gate but has about three times the output drive capability.
It
has a short circuit protection network such that accidental grounding of the output will not
damage the circuit.
Input Loading
2 unit loads
Output Drive Capability
A-12
25 unit loads (capable of also driving 250 pf total capacitance with delays as
specified)
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