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NAND TYPE 1 PAC, MODEL DI-335
The NAND Type 1 PAC, Model DI-335 (Figures A-75 and A-76), contains 10 in-
dependent Z-input NAND gates.
Each gate performs the NAND function for positive logic
(+6v =ONE, Ov =ZERO).
For negative logic, it becomes a NOR gate.
Two of the 10 gates have separate load connections available at the PAC terminals.
Outputs of these gates can be tit:;/d together, using a single load resistor, without loss of output
drive capability.
INPUT AND OUTPUT SIGNALS
Inputs. - - When both inputs to a gate are +6v or not connected, the output is at
ground.
When any input is at ground, the output is +6v.
Load. -- This point is internally connected through a collector load resistor to+6v.
Collector Output. - - The collector output must be connected to at least one load
resistor, either internal or external to the module.
Output. - - Each output terminal is internally connected to a collector load re sis tor.
If an output is connected to load points or other outputs, the output drive capability of the
structure is reduced.
SPECIFICATIONS
Frequency of Operation (System)
DC to 5 me
Input Loading
l unit load each
Fan-In
Refer to general specifications.
Output Drive Capability
8 unit loads each
Outputs in Parallel
Refer to general specifications.
APPLICATIONS
Circuit Delay
(Measured at+ 1. 5v, averaged over two
stages)
30 nsec (max)
Current Requirements
+6v:
110 ma (max)
Power Dissipation
0. 67w (max)
Handle Color Code
Red
The NAND gates operate on levels, pulses, or combinations of both.
Two gates can
be wired back-to-back to form a de set-reset flip-flop.
The two gates with separate load outputs form standard NAND gates when the load
and collector output terminals are connected.
When the collector outputs of gates are con-
nected in parallel as in Figure A-77, the AND-OR-INVERT function is performed.
At the
point where the outputs are tied together, an AND operation with logic ONE s (OR operation
with logic ZEROs) takes place.
A-133
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