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The buffer register is a combination scrirl.l and parallel shift register.
WIH·n trans-
ferring data in from the signal line, character information is transmittt>cl via thv ASR
encoder/ decoder.
Transferring data out to the ASR is routed th rough the buffer register
and ASR encoder/decoder.
The SKS logic generates the device ready signal in response to any
of
the
ASR
SKS
instructions.
(See Programmers Reference Manual, 3C Doc. No. 130071628.) The SMK
logic generates a program interrupt request when the interface is ready and the SMK flip-
flop is set.
The stop logic monitors the contents of the buffer r egis te r for an X -0 FF character.
When this character is present, a stop flip-flop is available for one character time for
program test.
OPERATION
The following detailed discuss ion contains a des er iption of interface opera ti on in the
input and output modes, each based on a timing diagram and LBDs 340, 341, and 342.
The
input mode discuss ion is given first.
Input Mode
Assume that an OCP '0004 (Enable ASR in Input Mode) is issued.
As a result of this
instruction, the interface logic receives an OCPLS- signal and a teletype address code (see
LBD 342).
The OCPLS- signal is used to generate signal OCPXX+.
The address code
generates signal TYADX-.
OCPLS- is used, in conjunction with TYADX+ and ADBl 0-, to generate signal TYICP-
and to reset the output mode flip-flop TYOUT, LBD 342
£5.
TYICP- generates PREST-
which clears the buffer register and resets the TYRDY, TYKOX, TYKlX, and TYCFB flip-
flops.
This initializes the interface for input mode operation.
The next step is for the operator to strike a key on the ASR.
This action causes
TYDAT- to become passive (LBD 341 Jl 0), and in turn causes TYDTA+ to become active.
(See Figure 2-31 for Input Mode Timing Diagram.)
This causes the busy flip-flop (TYBSY)
to be set (LBD 340 L4).
With TYBSY set, the clock is started (LBD 340 Al).
Note that all the conditions for the generation of the first of the two-phase clock pulses,
TYKl P, are present at the input of gate LlAl 7C (LBD 340 El 0).
The trailing edge of
TYKl P+ is used to set the TYCFA flip-flop in conjunction with signals TYSTP- and TYCAL+.
With reference to Figure 2-31, note that as the clock cycles,
the TYKOX flip-flop is
reset, enabling the generation of the second of the two-phase clock pulses, TYK2P (LBD
340 El 1 ).
With all inputs to gate LlC 14C true, the first of nine shift pulses is generated
(TYSFT).
The function of this pulse is two-fold.
First, it shifts data bits into the buffer
register, and second, it keeps track of the number of data bits shifted into the buffer
register.
The first shift pulse always stores a space in the LSB (least significant bit) of the
buffer register.
(When this space is propagated through the buffer register it is stored
2-48
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