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A great deal has occurred in the previous paragraphs.
Let us temporarily stop time
and examine the events more closely to see the logic behind what has happened.
First, the
ready flip-flop (TYRDY) was reset to inform the CPU that the interface is involved in a data
transfer.
This condition is tested by an "if ready" SKS.
Second, the busy flip-flop (TYBSY)
is set.
The condition is tested by an "if not busy" SKS.
Now the CPU knows that the ASR
is both "busy" and "not ready" and cannot accept or provide data until the present operation
is terminated.
The busy flip-flop enabled the clock to run, permitting the sequence control logic to
initialize prior to the acceptance of data from the output bus.
When the character is trans -
£erred from the CPU to the interface, the OTB gating logic stores the character in the buffer
register, enabled with internal control signal TYOTP+.
Now consider what remains to be done.
The buffer register contains a character
that needs to be transferred to the ASR.
Since the ASR input must be serial, some means
of serial entry must be provided.
Further, it is important to keep track of the data bits
in order to determine when the last bit has been routed to the ASR.
This is implemented
by shifting the data bits, one at a time, into the TYDRO flip-flop.
Since the signal driver/
receiver is sensitive to the state of TYDRO, each bit shifted into TYDRO is sent to the
ASR as a mark or space.
As the data bits are shifted through the buffer register, ZEROs
are pushed into the buffer register, one at a time, as a function of the shift pulses and
the reset state of the TYCBC flip-flop.
Now let time start again to generate the first
shift pulse.
In examining the inputs to gate L lA 1
7
B, note that the states of these inputs are
such that signal TYSFT+ (shift pulse) is generated.
TYSFT+ shifts the contents of the
buffer register down one position and on its trailing edge, resets the TYCBC flip-flop.
(See LBD 341.)
This unconditionally puts a ONE in TYDR8 and sends the first data bit to
the ASR via the signal driver/receiver (LlA16). Each successive shift pulse enters a ZERO
into TYDR8 and shifts the data bits through the buffer register to the ASR.
With the generation of the ninth shift pulse note that the inputs to gates L 1 Bl3F, C,
and D reflect the contents of the buffer register.
This causes signal TYRCF- to be generated
which in turn resets the TYCFA flip-flop, inhibiting the generation of additional shift pulses.
As a result, a marking condition is presented to the ASR.
The operation is terminated when the TYSTP and TYCFB flip-flops are set. The mutual
dependence of these two flip-flops causes them both to become reset after the combination
of TYCFB and TYDRO resets the busy flip-flop which in turn stops the clock.
Dummy Cycle
The dummy cycle is necessary to give the ASR enough time to respond to a change from
input mode to output mode.
Figure 2-33 is a timing diagram that illustrates what happens
in the interface when an OTA is given immediately after an OCP and when an OTA is given
after the dummy cycle.
Observe that when the OCP is issued, the busy flip-flop is set and
the clock is started.
The OCP also causes TYDRO to be set and the remainder of the buffer
register is reseL
This makes TYRCF- true, resetting the TYCFA flip-flop (LBD 340).
2-52
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