Local Storage Registers (Lsr) - IBM 5410 Maintenance Manual

LOCAL STORAGE REGISTERS (LSR)
The LSRs are a group of 9 bit registers (one byte plus parity)
that serve as halfword address registers. They have the
following primary functions:
• Maintaining sequential instruction addresses
• Maintaining current operand addresses during instruction
execution
• Maintaining 1/0 data area addresses
In addition, LSRs have the following secondary functions:
• Index registers for modification of operand addresses
• Interim storage for data, length count, and program con-
dition status referred to as 'scratch pad' type of storage
Figure 2-41 lists the LSRs for the base system and available
features. To read out data only 'select' is needed. To write,
'data', 'write hi or write lo' and 'LSR select' are needed. The
following is a list of the functions of the base system LSRs:
lnstroction Address Register-Used to keep track of the
storage of the next sequential instruction byte to be read
out of storage. At the beginning of each I-cycle, the address
in the IAR is gated into the SAR to be decoded. During
each I-cycle, the contents of the IAR is incremented by 1
in preparation for the next I-cycle.
A Address Register-The AAR keeps track of the storage
address of the next byte to be addressed in the A field.
During I-cycles, the A field address is taken from the in-
struction and loaded into the AAR. At the beginning of
each A-cycle, the address in the AAR is gated into the SAR.
During each A-cycle, the contents of the AAR is decre-
mented by 1 in preparation for the next A-cycle.
B Address Register- The BAR keeps track of the storage
address of the next byte to be addressed in the B field.
During I-cycles, the B field address is taken from the
instruction and loaded into the BAR. At the beginning of
each B-cycle, the address in the BAR is gated into the SAR.
During each B-cycle, the contents of the BAR is normally
decremented by 1 in preparation for the next B-cycle.
Index Register 1 and Index Register 2- These registers can
each store a t\\o byte address to be used in indexing oper-
ations. During an indexing operation, the CPU automatically
adds the single byte displacement from the instruction to
the contents of XRI or XR2 to obtain the actual B or A
2-34
LOCAL STORE REGISTERS (BASE SYSTEM)
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
LOCAL STORE REGISTERS (BASE SYSTEM)
Prog Level 1 Instr Address Reg
P1 - IAR
Prog Level 1 Address Recall Reg
P1 - ARR
A Address Reg AAA
Spare SPARE 1
Prog Level 1 Index Reg 1
P1 - XR1
Prog Level 1 Status Reg*
P1 - PSR
B Address Reg BAR
MFCU Print Data Address Reg MPTAR
Prog Level 1 Index Reg 2
P1 - XR2
Line Printer Data Address Reg LP DAR
Line Printer Image Address Reg LPIAR
MFCU Punch Data Address Reg MPCAR
MFCU Read Address Reg MR DAR
Length Count Reg LCR Data Recall Reg ORR
Interrupt Level 1 Instr Address Reg IAR -1
Interrupt Level ·1 Address Recall Reg ARR -1
* PSR Lo
PSR Hi
is used as the Condition Recall Register, CAR;
is used as the Length Count Recall Register, LCRR.
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
01-14
15
16
LOCAL STORE REGISTERS (FEATURE
1)
Prog Level 2 Instr Address Reg P2- IAR
Prog Level 2 Address Recall Reg
P2-ARR
Bi-Sync Comm Adapter Address Reg ASCAR
Serial 1/0 Channel Address Reg SIAR
Prog Level 2 Status Reg*
P2- PSR
Interrupt Level
4
Instr Address Reg
IAR-4
Interrupt Level 4 Address Recall Reg
ARR-4
Disk File Control Address Reg
DFCR
Prog Level 2 Index Reg 2 P2- XR2
Spare SPARE 4
Interrupt Level 2 Instr Address Reg IAR- 2
Interrupt Level 2 Address Recall Reg
ARR-2
Disk File Data Address Reg
DFDR
Prog Level 2 Index Reg 1
P2- XR1
Interrupt Level 0 Instr Address Reg
IAR-0
Interrupt Level 0 Address Recall Reg
ARR-0
LOCAL STORE REGISTERS (FEATURE 2)
Spare
Interrupt Level 3 Instr Address Reg
Interrupt Level 3 Address Recall Reg
Spare
lAR-3
ARR-3
Figure 2-41. Local Storage Registers