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low order of the IAR is decoded to determine if it con-
tains F /F (Figure 3-9). If it does, a one is loaded in the A
register to substitute for the carry. The high order position
of the IAR is entered into the B register and the two are
added in the ALU. The ALU results are then loaded in the
high order position of the IAR. At clock 5 and 6 time the
low order position of the IAR is incremented in the normal
manner.
DM 5-040 contains the circuit description.
Execution Cycles
Because only one byte at a time can be removed from or
placed into main storage, two cycles per byte are required
when controlling data between two different storage
locations. During the A cycle, the A field byte is removed
from storage and retained. The B cycle is then used to
remove the B field byte from storage and, depending upon
Gate LSR Hi To B
B
. . -.Register
Bi nary Subtract
A Register
LSR
Hi
Step 1
Clock 1and2
A
egiste
.._
___ _
LSR .._.._se_l_ec_t_l_A_R_
Lo
LSR Write Hi
Decode
Miscellaneous
---.,f
F/F
Bit
7
to A
Figure 3-9. 1-X Cycle-Incrementing IAR
3-6
the particular operation, to determine what to do with
each byte.
The B cycle operation is covered under the individual
operations but since the A cycle data flow is the same,
regardless of the operation,
it
can be covered as a separate
topic. Some operations require the condition register to
be reset to equal during the first A cycle and some require
the use of sign control for the A field character, but the
basic data flow remains the same.
•
A Cycle
• Store A field byte in DRR.
The first step in an A cycle, as in all cycles, is to address
the core storage location to be used during that cycle.
At clock 0 time the contents of the AAR are transferred
to the SAR in the same manner that the IAR was transferred.
Gate LSR Lo To B
B
Register
LSR
Hi
Step 2
Clock
5
and 6
A
Register _ _ _ __
: Miscellaneous
Bit 7 to A
Binary Complement
A Register
LSR
~Se-le_ct_l_A_R_
Lo
LSR Write Lo
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