IBM 5410 Maintenance Manual page 62

Processing unit
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The equal, low, high, and binary overflow conditions reflect
the result of executing the last instruction which affected
them (one of the following):
• Add zoned decimal
• Zero and add zoned
• Subtract zoned decimal
• Edit
• Compare logical characters
• Add logical characters
• Subtract logical characters
• Add to register
• Compare logical immediate
The decimal overflow or the test false condition is set by
the first instruction which results in that condition and
can be reset by one of the following:
• Branch on condition
• Jump on condition
Operation
Logical
Add
• Load register (PSR) instruction {loads the respective bit
position to zero)
• System reset
System reset initializes the condition register to:
• Equal condition
• Not overflow condition
• Not test false condition
Loading of the condition register may be from the ALU
output, but normally the bits are set individually in the
latches by the CPU logic as a result of instruction execution.
When the CR contents is needed for program testing, its
output is fed to the A register and into the ALU.
The lower six bits of the program status register (PSR)
contain the image of the condition register for the specific
program level. PSR is used to save and to initialize con-
dition register settings of the individual program levels.
Figure 2-43 shows the condition register settings.
The conditions of the 1/0 attachment logic are stored in
registers in the attachment and do not affect the state of
the condition register.
Branch or
Decimal
Compare
Logical Add
Test
Jump on
Condition
Bit
Arithmetic
Sub Logical
to Register
Edit
Bits
Condition
Equal
7
Result is
First
Result is
Source is
Zero
Operand is
Zero
Zero
Equal to
Second
Low
6
Negative
First
No Carry and
Negative
Operand is
Non-Zero
Lower than
Result
Second
High
5
Positive
First
Carry and
Positive
Operand is
Non-Zero
Higher than
Result
Second
• '
-
-
.
I
0ecima1
'
::;,
l
Ove1f?ow
Overflow Reset
Overflow
if Tested
Test
3
Test
Test False Reset
False
False
if Tested
Binary
2
Overflow
Overflow
Figure 2-43. Condition Register Settings
5410 TO
2-37
E

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