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field address. The contents of the index registers is not
changed as a result of the addition. The resulting address
is placed in the BAR or the AAR.
Address Recall Register-On a branch instruction, the ARR
contains the 'branch to' address. On a decimal instruction,
the ARR retains the starting address of the B field in the
event recomplementing is required. On an insert and test
characters instruction, the ARR contains the address of the
first significant digit encountered.
Length Count Register- The LCR is a one byte register that
contains the length count of the Band A fields. It gets
decremented by 1 on each B-cycle except the first one.
Data Recall Register-The DRR is a one byte register that
provides temporary storage for the data character read out
of storage during each A-cycle. It is also used to store the
Q
code of single address instructions.
Program Status Register- The high byte of the PSR is used
as the length count recall register (LCRR). The LCRR
is used only during a recomplement operation. It stores
the length of the data fields and is decremented on each
recomplement cycle except the first. The low byte of the
PSR is used as the condition recall register (CRR). The
CRR is used to store the contents of the condition register
when changing program levels (used only with dual pro-
gramming).
MFCU Read Data Address Register-The MRDAR keeps
track of which storage position is to be addressed next
while reading data from a card into the card read area in
core storage.
MFCU Punch Data Address Regi$ter- The MPCAR keeps
track of which storage position on the MFCU print data
area is to be addressed next during a punch operation.
MFCU Print Data Address Register- The MPT AR keeps
track of which storage position in the MFCU print data
area is to be addressed next during an MFCU print operation.
Line Printer Data Address Register-The LPDAR keeps
track of which storage position in the line printer data
area is to be addressed next during a print operation.
Line Printer Image Address Register- The LPIAR keeps
track of which storage position in the chain image area
is to be addressed next during a print operation of the
line printer.
Interrupt Level 1-The IAR-1 contains the address of the
next sequential instruction byte to be read out of storage
during an interrupt level 1 operation.
Interrupt Level 1 Address Recall Register- The ARR-I
has the same function as the ARR, but is active only during
an interrupt level 1 operation.
The registers are paired (Figure 2-42) to give an LSR Hi
(the high-order byte) and an LSR Lo (the low-order byte).
Only one byte can be written into an LSR at a time. To
write into an LSR, it is necessary to activate the select
line for a pair of registers and the 'LSR write Hi' or 'LSR
write Lo'. All 18 bits for the LSR selected are available at
the output of the LSR array. These bits can be gated to the
SAR (18 bits), the B register (9 bits), and the A register
(9 bits) for modification of the addresses in these registers.
DM 4-070 shows the circuitry for the LSRs.
LSR select and write lines are normally controlled by the
CPU. However, during an 1/0 cycle, the 1/0 attachment
can control the select lines for the LSR assigned to it.
DM 4-072 shows the LSR select circuitry and DM 4-076
shows the LSR select 1/0 circuitry.
5410TO
2-35
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