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Subtraction is done in the same way as binary subtraction
as long as the minuend (B register) is larger than the subtra-
hend (A register). But, because the ALU is capable of
handling digits up to 15 (F in hexadecimal) and in this case
the digits have a maximum value of 9, the ALU reaches an
incorrect decimal result when it becomes necessary to bor-
row from the next digit (A register larger than B register).
This difference of 6 must be subtracted from the result in
order to reach a correct result (Figure 2-33). The decimal
correct circuits are activated by the carry from the bit 4
position. Figure 2-34 shows the data flow for decimal
subtraction and contains a table of the bit correction for
the legitimate decimal characters.
Bits 0 to 3 of the low order decimal character contains the
sign of the field. The ALU output for bits 0 to 3 is deter-
mined by the sign control circuits and is covered under the
individual operations.
B Register
B Larger Than A
A Larger than B
8-3
3-8
222
2
B register 1000
B
Register 0011
A register 0011
A Register 1000
Carry 111
Carry
Total
0101
Total
1011
Note:
Subtract and complement
functions affect only the
Total
digit portions. The zone
Decimal Correct
portion is not affected.
Carry*
Corrected Total
*Mathematical carry; not done by carry circuit
Figure 2-33. Decimal Correction
ALU
Latches
7 through 4
Internal Bits 7 through 4
Decimal
. . . . - . . - - - - - - - • c o r r e c t • - •
FL
AR ister
Decim
I
Instruction
Figure
2-34. DecimiiJ .:;
;btract
Data Flow
to
Bit 3
A
Circuits
Input
Output
Bits
Bits
4667
4567
1111
1001
1110
1000
1101
0111
1100
0110
1011
0101
1010
0100
1001
0011
1000
0010
0111
0001
0110
0000
2
1011
0110
1
0101
5410 TO
2-29
E
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