IBM 5410 Maintenance Manual page 79

control' changes this to EBCDIC. After the first byte of
each field, all zone bits ( 1111) are provided for each
character. During the first B cycle, the sign of the B field is
entered into storage.
During clock 1 and 2 of the first A cycle, the condition
register is reset to equal. Then in the first B cycle, the
'CR lo/hi' latch is set by the result sign (lo for minus, hi
for plus). However, if no numeric output occurs from the
ALU (all zeros), the condition register remains set to equal.
If, during any B cycle, a non-zero ALU output occurs, the
result can no longer be equal and the equal condition is
reset. The setting of the 'CR lo/hi' latch is then used to
determine the CR setting.
If the CR equal condition has not been reset before the
last B cycle and the 'CR lo/hi' latch is set to lo (minus)
the result is minus zero. All zero results are considered
plus so 'recomplement cycle' is activated to recomplement
the results.
If the operation is an add function (decimal complement
A register) and no carry occurs from the high order position,
the CR decimal overflow condition is also set. This is an
indication that the result is too large to be contained in the
B field. Figure 3-21 shows the significance of all the CR
settings.
DM 5-_l 00 contains the circuit description.
Gate SOR to 8
Main S
Storage D
R
Figure 3-22. Recomplementing
3-14
8
Register
Store New
Recomplement
Addressing for recomplement cycles is controlled by the
ARR which contains the low order address of the B field
(refer to 1-Hl and 1-Ll cycles). The ARR is decremented
each recomplement cycle in the same manner that the AAR
and BAR are decremented in other operations.
'EA eliminate' is active through the entire recomplement
operation causing continuous B cycles. Each byte is read
from storage and loaded into the B register (Figure 3-22).
The A register has a 1 forced into it on the first recom-
plement cycle and is left with all zeros for the remainder of
the cycles. Both the A and B registers are decimal com-
plemented.
The length of the field is determined by the LCRR which
was loaded during the 1-Q cycle. Decrementing of the
LCRR is the same as for the LCR in a decimal add or
subtract operation (Figure 3-20).
Condition Decimal
Register
Equal
Low
High Overflow
ALU
Result Result Result Result too
result is zero is minus is plus large for
field
Figure 3-21. Condition Register-Add or Subtract Zoned Decimal
Miscellaneous Bit 7 To A
(1st Recomplement Cycle Only)
A
Register
.....
~--~~~~~---'
Oeci mal Subtract
Decimal Complement A Register
Decimal Complement 8 Register