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select one of the two index registers. Bit 7 only being on
selects XRl, bit 6 only being on selects XR2. Data is trans-
ferred from the storage position addressed by the IAR to the
B register, through the ALU, and into the high order posi-
tion of the selected index register. The IAR is incremented
and during the I-LI cycle the process is repeated for the low
order position of the index register.
A.
three byte format
requires going through only one IX cycle. Data is trans-
ferred from the storage location address by the IAR to the
B register and at clock 3 time is added to the contents of
the selected index register (bits 0 through 3 of the op code).
Bits 6 or 7 of the Q code selects one of the index registers
at clock 4 time and the sum in the ALU is loaded into that
register. The IAR is incremented for the next operation.
DM 5-109 contains the circuit description.
Branch On Condition-BC
• Condition register is tested for the condition specified
.... in Q code.
• Branch to address is placed in ARR.
• ARR/IAR interchange if tested condition is satisfied.
The branch on condition operation loads the two byte
branch to address into the ARR. If the condition specified
in bits 2 through 7 of the Q code is satisfied (Figure 3-51 ),
an IAR/ARR interchange occurs at op end. The ARR is
then used as the IAR.
Bit 0 of the Q code is used to specify if the branch is to be
performed on condition true or condition false. If bit 0
is on and at least one of the conditions specified by the Q
code is present, the branch is performed. If bit 0 is off and
all
conditions specified by the
.0
code are missing, the branch
is performed.
OBit
Condition Tested
0
Presence of Condition
Noto
Absence of Condition
7
Equal
6
Low
5
High
4
Decimal Overflow
3
Test False
2
Binary Overflow
Figure 3-51. Branch On Condition-Q Code
3-32
During the 1-Q cycle, the Q code data is transferred from
storage, through the B register, and into the ALU. The
contents of the condition register is decoded and enters the
ALU through the A register. An ALU AND function is
performed (both input bits must be the same to get an
output}, and the output is checked for non-zero. The
result is placed in the Q register. B register bit 0 is used to
. determine if an ALU sum of zero or not-zero is needed to
satisfy the branch condition. Figure 3-52 shows the function
of each Q code bit when testing the condition register. If
the branch condition is satisfied, the IAR/ ARR interchange
latch is set (Figure 3-53). The LSR switching does not
occur, however, until op end.
During the 1-Hl cycle, the ARR is selected and the high
order position of the branch to address is transferred from
storage through the B register, ALU and into ARR high.
The IAR is incremented and the process is repeated for the
low order position.
DM 5-130 contains the circuit description.
COMMAND INSTRUCTIONS
• Load operation code into op register.
• Q code used to define command.
• Control code is third byte of instruction and contains
additional information pertaining to the command.
I-cycles for command operations are three cycles in length;
first, an I-op cycle transfers the operation code from main
storage to the op register. Second, an 1-Q cycle transfers
the Q code into the Q register and DRR. If the operation is
a branch or jump, the condition register is also tested for
true or false. Third, an 1-R cycle is then used to transfer
from storage the control code needed to execute the
command. The details for use of the control code are
covered under specific operation descriptions.
Jump On Condition-JC
• Condition register is tested for the condition specified
in the Q code.
• If the tested condition is satisfied, control code is added
to IAR for next sequential instruction.
The jump on condition operation is similar to branch on
condition except for the instruction address modification.
If the condition register contents satisfy the condition
specified in the Q code (Figure 3-51 ), the control code byte
is added to the IAR.
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