Instruction And Execute Cycle - IBM 5410 Maintenance Manual

Basic Data Flow
The system storage address register (SAR) addresses the
storage unit (see 'Addressing System' for details). When
the system signals the storage unit with read call/write call,
a read cycle is started. The data located at the specified
address is read out to the storage data register (SDR) and
placed on data lines to the system. The read cycle is com-
plete and the storage clock stops after approximately 600
ns. Data flow is shown in Figure 1-5.
The data read out may be placed back into the addressed
location, or new data may be placed into that storage
position. When storing new information, 'store new' causes
the data latches to be cleared prior to their setting with new
data. Read call/write call starts a write cycle and the infor-
mation in the data latches is transferred to core storage.
The write cycle is complete and the storage clock stops
after approximately 600 ns.
Instruction and Execute Cycle
• I-cycles read out instructions from storage.
• A cycles and B cycles execute the instruction.
There are two types of machine cycles used in the internal
operation of the CPU. These are instruction cycles (I-cycles)
and execute cycles.
I-cycles are used to move the instructions from storage to
the various registers required to execute the instruction.
If the instruction does not require additional use of main
storage after the completion of I-cycles, such as a branch
·instruction, the operation is completed without execute
cycles. However, most operations require the use of data
from one or two main storage fields. Execute cycles are
used to manipulate this data to perform the operation.
Sense Bits
Interface
\-- _ _ _!imi".!!_and
~terloc~
Signals
SAR
SYSTEM
Figure 1-5. System-Memory Data Flow
1-8
Store Bits
Timing
and
Control
Bits 1 and 2
Address
Decode and
Drive
MEMORY
Storage
Data
Register
Write Read
Inhibit Sense
Array