Table of Contents
Advertisement
Main
S
Storage
D
R
B
Gate SOR to
B
Select ORR and LCR LSR
LSR
LSR Write Lo
Hi
(ORR)
Figure 3-10. A-Cycle Storage to DRR Transfer
Gate LSR Lo To B
B
LSR
LSR
High
Lo
Step
1
Figure 3-11. Decrementing AAR
Lo
A
Register--~
Miscellaneous
Bit
7
to
A
Select AAA
LSR Write Lo
No data is transferred during clock 1 and 2 times as the
CPU waits for the data to read from core storage and enter
the SDR. During clock 3 and 4 times the byte is trans-
ferred through the B register and ALU and stored in the
DRR (Figure 3-10). At clock 5, 'read write pulse' stores
the SDR contents back into the same core storage location
to regenerate the A field character.
The rest of the cycle is then used to decrement the AAR so
that the next position of the A field can be addressed if
necessary. Figure 3-11 shows that a 1 is subtracted from
the AAR. Two steps are required because of the possibility
of a carry from the low order to the high order position.
Refer to the operation flowcharts in the IBM 5410 Pro-
cessing Unit Diagrams, SY31-0202, for the circuit
description.
Gate LSR
Hi
to
B
B
LSR
LSR
Select
AAR
~i
Lo
LSR
Write
Hi h
Step 2
5410TO
3-7
E
Advertisement
Table of Contents
