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Main
S
B
torage
0
•-•-fRegister•-•
R
Gate SOR to
B
Load
Q
Register
a
·---~
Register
_Se_l_ec_t_O_R_R_an_d_L_C_R _ _ _ _ LSR
LSR
Select PSR (LCRR)
Hi
Lo
LSR Write Hi
(LCR and LCRR)
Figure 3-4. 1-Q Cycle-Stllrage to Registers Data Flow
1-H 1 and 1-L 1 Cycles
1-Hl and 1-Ll cycles are the same as the I-op and 1-Q
cycles except that the data bytes, B field address, are stored
in the BAR. During the 1-Hl cycle, the first byte is stored
in the high order position of the BAR (Figure 3-5). The
following cycle, 1-Ll, stores the second byte in the low order
position of the BAR. For decimal instructions, the bytes
are also stored in the ARR.
DM 5-030 contains the circuit description.
l-H2 and J-L2 Cycles
I-H2 and I-L2 cycks . .re the same as 1-Hl and 1-Ll cycles
except the address b:J tes are stored in the AAR.
DM 5-030 contains the circuit description.
Main
S
Storage
0
•-•-1
R
Gate SOR To B
Select BAR
LSR Write Hi
B
egister
LSR
LSR
Hi
Lo
Figure 3-5. 1-Hl Cycle-Storage to BAR High
5410TO
3-3
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