Indexing - IBM 5410 Maintenance Manual

Indexing
The need for 1-X cycles is determined by the bit structure
of bits 0 through 3 of the operation register. An 1-Xl
cycle results from the presence of either bit 0 or bit l, but
not both; an I-X2 cycle from either bit 2 or 3, but not both.
The bit which is present also determines the index register
used (Figure 3-6).
Operation Index
Cycle
Register Register
Bit Selected
1 XR1
l-X1
0 XR2
3
XR1
l-X2
2 XR2
Figure 3-6. Index Register Selection
Gate SOR to B
Main S
Storage D
R
B
Binary Subtract
Binary Complement
A Register
XR1 Selected LSR LSR
(or XR2 Selected)
Hi Lo
Clock 3
Figure 3-7. 1-Xl Cycle-Indexing BAR Low
3-4
During an 1-Xl cycle the IAR is selected and loaded into
the SAR in the same manner as for other instruction cycles.
At clock 3 time the low order position of the selected fndex
register is entered into the A register (Figure 3-7). The
address byte is read from main storage and is gated from
the SDR to the B register. The two bytes are then added
in the ALU. At clock 4 time, the index register is dropped
and the BAR is selected. The ALU contents are then
written into the low order position of the BAR.
If
a carry
results from the computation, it is added to the high order
position of the BAR during clock 7 and 8 time (Figure 3-8).
The high order position of the selected index register is
gated into the B register and added in the ALU. At clock
8 time the results are written into the high order position
of the BAR.
If
the operation is a decimal or branch oper-
ation, the results are also stored in the ARR. An I-X2 cycle
operation is the same as an 1-Xl except that the results are
written in the AAR.
Since clock 7 and 8 times are normally used to increment
the high order position of the IAR, the incrementing se-
quence is changed for an 1-X cycle. Because the high order
position of the JAR can be affected only by a carry from
the low order position, the CPU looks ahead to determine
if a carry will be needed. During clock 1 and 2 times the
Gate LSR Lo Normal To A
A
B
Register
Binary Subtract
Binary Complement
A Register
Se __ le_c_t_B_A_R ____ M LSR LSR
LSR Write Lo
Hi Lo
Clock 4
A
Register