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the device in the CPU (Figure 3-63).
If more than one de-
vice is requesting an interrupt, only the highest priority
interrupt latch will be turned on.
With any interrupt latch on, the selection of the normal
IAR/ARR (Pl or P2) is blocked and the IAR/ARR for the
active interrupt level latch is selected (Figure 3-64). The
interrupt request latch in the device attachment stays on
until an SIO with the proper control code resets it (Figure
3-63).
Interrupt
Latch
FL
OR
Any Interrupt Level
Being
Serviced
N ..___ _ _
A
P1 IAR
ARR
Selected
A
Select IAR-ARR
Interrupt
Figure 3-64. Interrupt-JAR/ARR Selection
Gate SOR To B
Main
S
Storage
D
R
B
Register·•--
LSR Write Lo
DM 5-230 contains the circuit description.
Load 1/0-LIO
• Moves two bytes from storage to register selected by
1/0 attachment:
• Follows command format if device is busy or needs
attention.
• A Q code of 0/0 results in a no op condition.
The load 1/0 instruction is a single address instruction that
can be executed only if the addressed device is not busy
and does not need attention.
If the instruction cannot be
executed it follows a command format and loops on the
instruction in the same manner as an SIO instruction.
When it can be executed, the load 1/0 instruction removes
two bytes from storage and loads them into a register
selected by the device attachment (Figure 3-65). The
register may be located in the attachment or may be an
LSR in the CPU. In either case, two B-cycles are required
to remove the bytes from storage.
DBO
----i..----------t
LSR
LSR
1st
LSR Select (Device Address Register)
B
Cycle
Figure 3-65. Load 1/0 Data Flow
3-44
Hi
LSR Write Hi
N
Lo
LSR
Select
Triggers
FF
LSR Select Lines
FF
from Attachments
----"'
LSR
Select
Decode
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