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Q
Code Bit
Register Selected
6
XR-2
7
XR-1
Figure 3-48. Load Address-Index Register Selection
The load address instruction performs one of two possible
operations, depending on the instruction length. If the in-
struction is four bytes long (Figure 3-49), the last two bytes
of the instruction are taken from storage and loaded into
the index register selected by bits 6 and 7 of the Q code
(Figure 3-48). If the instruction is three bytes long (Figure
3-50), the last byte of the instruction is taken from storage,
added to the contents of the index register selected by bits
0-3 of the op code, and then loaded into the index register
selected by bits 6 and 7 of the
Q
code.
A four byte format requires one 1-Hl cycle and one I-LI
cycle. During the 1-Hl cycle bits 6 and 7 of the
Q
code
Main
S
B
Storage
D
Register
Rlllmlllllli~
· - ·
Gate SDR To B
LSR Write Hi (l-H1)
LSR
LSR
LSR Write Lo (l-L1
l
Hi
Lo ·
XR1 Selected
(O
Bit
7)
XR2 Selected
(Q
Bit
6)
Figure 3-49. Load Address Data flow-Not Indexed
Gate SOR To B
Gate LSR Lo Normal To A
Main
S
B
Storage
D
R
Bi nary Subtract
Binary Complement
A
Register
XR1 Selected or XR2 Selected
-----------.i
LSR
LSR
(Selected by Op Code)
Hi
Lo
Clock 3
Figure 3-50. Load Address Data Flow-Indexed
A
B
Register - - -
Binary Subtract
Binary Complement
A Register
X R 1 Selected or X R2 Selected
(Selected by
Q
Code)
LSR
Hi
Clock 4
LSR
Lo
5410 TO
3-31
E
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