Table of Contents
Advertisement
disturbed. Any other registers (CR or index registers) used
during the interrupt must be stored at the beginning and
re-established at the end of each interrupt routine.
The interrupt routine being performed is established by the
interrupt priority latches. As in cycle steal, the highest
interrupt level device takes precedence over lower level
devices. Thus, it is possible for an interrupt routine to
interrupt a routine of a lower priority device. However,
each device maintains its interrupt request until it is satisfied,
so the lower priority device finishes its routine upon com-
pletion of the higher level routine.
The stored program controls the ability of a device to
interrupt by enabling and disabling the device through SIO
SIO Inst
l·R Cycle
instructions. Once an interrupt has occurred, the interrupt
routine is also ended by an SIO instruction.
During the 1-Q cycle, device selection occurs in the same
manner as any SIO instruction. Then at clock 5 of the 1-R
cycle, the control code is sent to the device attachment on
DBO (Figure 3-63). The control code is decoded by the
device attachment to turn on the 'interrupt enable' latch.
This latch remains on until a disable control code is sent in
another SIO instruction.
If the device has a need to interrupt, the 'interrupt request'
latch is turned on. At the end of the operation being per-
formed in the CPU interrupt poll is sent to the device. This
activates the 'DBI bit' line to turn on the interrupt latch for
Op End
Interrupt
Latches
FL
Clock 5
Op End Gate
Interrupt Poll
M/C Advance
A
DBO
I
Decode
Control
Code
Enable
Reset
Note: Actual logic varies with
the devices. This figure merely
represents the concept <1volved.
Figure 3-63. Interrupt Control
Clock
5
to
8
FL
FL
Device *
Keyboard
Console
Interrupt Request
DBI Bit and
Interrupt Latch
None
* By order of priority
5410 TO
3-43
Advertisement
Table of Contents
