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Cycle Steal Priority (CSP)
• Device requests cycle.
• CPU assigns cycle by device priority.
• 1/0 cycle can occur between any two CPU cycles.
Whenever an 1/0 device reaches a point in its mechanical
operation where it needs data from storage (write, print,
punch) or has data to send to storage (read) the device
requests an 1/0 cycle. An 1/0 cycle request can occur
during any cycle and is always granted by the CPU. More
than one 1/0 device may request an 1/0 cycle at the same
time so each device is assigned .a particular cycle steal
priority.
Cycle steal requests are generated by the attachments at
even clock times. Because of the internal circuit delays,
these lines are not sampled until the next clock pulse.
During the CPU odd clock times, requests for cycle steals
enter the CPU from the attachments on the 'priority request'
lines (Figure 3-59). These requests are entered into the
'priority request' latches and triggers.
If more than one
device requests an 1/0 cycle during the same clock time,
the bit triggers with the highest priority prevent the lower
priority triggers from being turned on. A request at a later
clock time resets the triggers and latches for any previous
request.
At clock 7D time, the bit structure for the highest priority
device among those requesting a cycle is sent to the devices
on the DBO, bypassing the DBO translator (Figure 3-59).
'Any CSP request' blocks the 'machine advance' pulse pre-
venting the CPU from advancing to the next CPU cycle.
Internal Circuit
Priority Rtmuest Lines
(3J_4,5,6
7)
Delay~
I
. . . -iiiiiilfliliiiiiiiiiliiiiiiilliiiiliiiliifi _ _ _ _ .....
1 - ,
(
~
J
1'
Lines become
5
active during
even clock ti mes.
Priority
Request
Latches
Clock 7
FL
Clock 5
Bits
Clock
3
P
Clock
1
0
1
2
Priority
~=;:J:I
~
.
ny CSP
Bits Request
CPU
-
-
-
Machine Advance
A
-
r--E
A
~°Q:c1ock
i
.--------~-
L__7 __
7D thru OC _]....__ _
____,
I
Priority
Cycle Steal
CPU
Request
Request line
Clock
Attachment
DBO Lines
1
3
7
Disk read/write
000010000
2
Spare
3
5
7
Printer
000000100
4
6
7
SIOC
000000010
5
Spare
6
3
5
BSCA
010010000
7
4
5
M FCU read/punch
110001000
8-10
Spare
11
3
3
1442
101010000
12
4
3
MFCU printer
101001000
13-19
Spare
20
7
1
Disk control
100100001
Figure 3-59. 1/0 Cycle Request-Priority Assignment
3-38
'1/0
Attachments
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