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SAR1
16-24K
0-SK
~
/ 1
/
I
Sense Bits (9-17)
24-32K
SAR1
Segment
Figure 2-18. Byte Control (32K BSM)
Write (Store)
A write cycle must follow every read cycle in order to
restore the cores to their original status {before the read
cycle). The read data bits are in the sense data latches
(SDR) and serve as inputs to control the Z drivers. However,
if this is a store new operation, 'store bit' lines from the
interface set the SDR latches along with the control line
'store new'. The 'store new' line causes the SDR latches to
be reset prior to their setting with new data. If SAR bit 2
was used for byte control on the readout, it is now used to
generate store byte I or store byte 2. These two signals
control the setting of the SDR latches 0-8 and 9-17 respec-
tively. SAR bit 2 selects only one of these two bytes and
the data contained in the other byte is gated back into
storage.
2-18
Strobe
Store New
SAR 2
Strobe
Store New
SAR 2
9
SR 071-73
9
SR 074-76
Storage Cycle Timing
Sense Bits
(0-8)
SAR 2
SAR 2
Sense Bits
(9-17)
OR To B Reg
9
The BSM is an asynchronous unit; that is, once started, it
runs independently. The CPU starts the storage cycle by
issuing the read call/write call signal. This turns on the
timing control latch and the read/write latch. The read/
write latch on defines this cycle as readout cycle. Late
in
the readout cycle the set reset latch is turned on; though
performing no function at this time, it ensures that the
next read call/write call resets the read/write latch.
Therefore, the following cycle is a write cycle. During the
write cycle, the set reset latch will be turned off, forcing
the following cycle to be a readout cycle.
The system must allow a minimum of 600 ns for each cycle
to be completed and also must hold the SAR {address lines)
active for both cycles. (Figure 2-19 shows the cycle timings.)
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