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1/0 INTERFACE
The CPU acts as a controller for all 1/0 devices operating
over a single 1/0 attachment interface. The 1/0 devices
operate in a cycle steal mode over an interface called
input/output channel (1/0 channel).
The 1/0 channel consists of:
1.
A set of powered signal lines which carry information
to and from the CPU, and
2.
Logic to establish cycle steal priorities.
The following priority is assigned to the devices using cycle
steal:
1.
Disk File Read/Write
2.
Spare
3.
Printer
4.
SIOC
5.
Spare
6.
BSCA
7.
MFCU Read and Punch
8.
Spare
9.
Spare
10.
Spare
11.
1442
2-38
12.
MFCUPrint
13.
Spare
14.
Spare
15.
Spare
16.
Spare
17.
Spare
18.
Spare
19.
Spare
20.
Disk File Control
This priority assignment makes it possible for the interface
to operate on a time sharing basis without the need for
1/0 buffers. Once a cycle steal request has been granted,
the attachment has complete control of the CPU for that
cycle.
DM 4-100 shows the 1/0 interface lines.
DBI Translator
The DBI translator is used during clock 2 and 3 time to
translate the 96-column card code into EBCDIC. The
translator is not used in every 1/0 cycle and if the 'translate
in' line is inactive, the 1/0 data is transferred to the A
register unchanged. Figure 2-44 shows a 'translate in' con-
version table.
DM 4-060 shows the circuitry for the DBI translator.
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