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Test Bits On Masked-TBN
• Activate 'CR test false' if bits present in the
Q
code are
not all present in the B address storage location.
The test bits on masked operation tests to determine if all
bits present in the Q code are also present in the B address
storage location.
If
they are not, the 'CR test false' latch
is turned on.
The operation requires a single B-cycle and uses the 'OR'
control line in the ALU (Figure 3-40). The Q code is trans-
ferred from the DRR to the A register and the B-field byte
is loaded into the B register. Any bit in the A register that
is not present in the B register gives a 'test false' output
(Figure 3-40). The results are not written into storage but
are used merely to set the condition register.
DM 5-050 contains the circuit description.
Gate SOR to B
Main
S
Storage
D
R
B
Register•--
Test Bits Off Masked-TBF
• Activate 'CR test false' latch if any bits present in the Q
code are also present in the B address storage location.
The test bits off masked operation tests to determine if all
bits present in the
Q
code are absent from the B address
storage location.
If
they are not, the 'CR test false' latch
is turned on.
The operation requires a single B cycle. The Q code is
transferred from the DRR to the A register (Figure 3-41).
The A register is binary complemented and the AND control
line in the ALU is used to give a 'test false' output for any
bit in the Q code which has a corresponding bit in the B
address byte. The results are not written into storage but
are used merely to set the condition register.
DM
5-050
contains the circuit description.
Gate LS A Lo Normal to A
(DAR)
A
LSR
LSR
Select ORR and LCR
Hi
Lo
(!
B Address Byte 0 1
: :Q:
~:
Q
Code Byte
0
Test False
Figure 3-40. Test Bits On Masked
3-26
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