ADLINK Technology AmITX-CF-G User Manual page 57

Mini-itx embedded motherboard with 8th and 9th gen. intel core i7/i5/i3 processors and intel q370/h310 chipset
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Feature
Serial Console Redirection ►
COM5
Console Redirection
Console Redirection Settings ►
COM6
Console Redirection
Console Redirection Settings ►
8.4.7.1. Advanced > Serial Console Redirection > Console Redirection Settings COM[1-6]
Feature
COM[1-6]
Console Redirection Settings
Terminal Type
Bits per second
Data Bits
Parity
Stop Bits
Flow Control
BIOS Setup
Options
Description
Submenu
Serial Console Redirection
Info only
Disabled
Console Redirection Enable or Disable.
Enabled
Submenu
The settings specify how the host computer and the
remote computer (which the user is using) will
(see Section 8.4.7.1)
exchange data. Both computers should have the
same or compatible settings.
Info only
Disabled
Console Redirection Enable or Disable.
Enabled
Submenu
The settings specify how the host computer and the
remote computer (which the user is using) will
(see Section 8.4.7.1)
exchange data. Both computers should have the
same or compatible settings.
Options
Description
Info only
VT100
Emulation: ANSI: Extended ASCII char set. VT100:
ASCII char set. VT100+: Extends VT100 to support
VT100+
color, function keys, etc. VT-UTF8: Uses UTF8
VT-UTF8
encoding to map Unicode chars onto 1 or more
ANSI
bytes.
9600
Selects serial port transmission speed. The speed
must be matched on the other side. Long or noisy
19200
lines may require lower speeds.
38400
57600
115200
7
Data Bits
8
None
A parity bit can be sent with the data bits to detect
some transmission errors. Even: parity bit is 0 if the
Even
num of 1's in the data bits is even. Odd: parity bit is
Odd
0 if num of 1's in the data bits is odd. Mark: parity bit
Mark
is always 1. Space: Parity bit is always 0. Mark and
Space
Space Parity do not allow for error detection
1
Stop bits indicate the end of a serial data packet. (A
start bit indicates the beginning). The standard
2
setting is 1 stop bit. Communication with slow
devices may require more than 1 stop bit.
None
Flow control can prevent data loss from buffer
overflow. When sending data, if the receiving buffers
Hardware RTS/CTS
are full, a 'stop' signal can be sent to stop the data
flow. Once the buffers are empty, a 'start' signal can
be sent to re-start the flow. Hardware flow control
uses two wires to send start/stop signals.
AmITX-CF-G
51

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