Component-Level Intellectual Property (Clip) - National Instruments PXIe-6569 Getting Started Manual

External Clk In
Front Panel
External Clk Out
Connector
(User Clock 1)
† The number of fixed direction LVDS input and output depends on the variant of the PXIe-6569.

Component-Level Intellectual Property (CLIP)

The LabVIEW FPGA Module includes component-level intellectual property (CLIP)
for HDL IP integration. FlexRIO devices support two types of CLIP: user-defined and
socketed.
User-defined CLIP allows you to insert HDL IP into an FPGA target,
■
enabling VHDL code to communicate directly with an FPGA VI.
Socketed CLIP provides the same IP integration of the user-defined CLIP,
■
but it also allows the CLIP to communicate directly with circuitry external
to the FPGA. Adapter module socketed CLIP allows your IP to communicate
directly with both the FPGA VI and the external adapter module connector
interface.
The PXIe-6569 ships with socketed CLIP items that add module I/O to the LabVIEW
project.
Refer to Configuring Your Adapter Module Using LabVIEW FPGA in FlexRIO
documentation for more information about CLIP.
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Control and Status
Si514 User Clock 2
Clocking
User Clock 0
LMK
Clocking
Reference Clk
8 SE IO (Bidirectional)
2 LVDS PFI (Bidirectional)
32 or 64 LVDS Input
†
32 or 64 LVDS Output
†
PXIe-6569 Getting Started Guide
Mezzanine
Connector