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CLIP Signal Name
LVDS_Data_Wr
LVDS_Data_Rd
Clk Out Inversion DO13
(HIHO)
Clk Out Inversion DO54
(All Out)
Clk Out Inversion DO29
(All Out)
Clk Out Inversion DO13
(All Out)
RX Data Clock (HIHO)
RX Data Clock Bank 44
(All In)
RX Data Clock Bank 45
(All In)
RX Data Clock Bank 46
(All In)
TX Data Clock
30
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Direction
To CLIP
From CLIP
To CLIP
To CLIP
To CLIP
To CLIP
From CLIP
From CLIP
From CLIP
From CLIP
From CLIP
PXIe-6569 Getting Started Guide
Data Type
U8
U8
Boolean
Boolean
Boolean
Boolean
Clock
Clock
Clock
Clock
Clock
Description
LVDS_PFI_Output_Ena
ble values:
1—Use
■
LVDS_PFI_Wr to
write to the PFI
data line.
0—Use
■
LVDS_PFI_Rd to
read the PFI data
line value.
Signals to read/write
data from the
LVDS channels. One
U8 control/indicator
represents the
serialized/deserialized
8-bit data for an LVDS
channel.
Inverts the generated
clock by applying a
180-degree phase shift
to the clock signal. The
generated clocks are
output on DO 13 (HIHO
and All Out), DO 29 (All
Out), and DO 54 (All
Out).
The acquisition clock
for acquiring the LVDS
input data. This clock
can be sourced from
an external DI line or
from the TX Data Clock.
Refer to
Figure 2
and
Figure 5
for additional
information.
The generation clock
for generating the
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