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PXIe-6569 CLIP
PXIe-6569 ships with two socketed CLIP options. These socketed CLIP options can
be used as-is or can be edited to suit your application.
Refer to the following table for more information about each socketed CLIP's
function and the signals used in each.
Note
Both PXIe-6569 CLIP items allow individual clock output inversion.
Table 2. PXIe-6569 Socketed CLIP Items
CLIP Name
PXIe-6569 Basic CLIP
PXIe-6569 SERDES Channel CLIP
PXIe-6569 Getting Started Guide
Description
Provides read/write access to all low-voltage
differential signal (LVDS) and single-ended
channels. You can access the LVDS data and
direction lines using a U64 or U32 data type
in which each bit position corresponds to an
individual channel. You can access the LVDS
PFI lines using a boolean data type and the
single-ended PFI lines using another boolean
data type. Generation channels are clocked by a
single generation clock signal, and acquisition
channels are clocked by a single acquisition
clock signal.
Provides read/write access to all LVDS and
single-ended channels using a channel-based
interface. You can access the LVDS data using
a U8 data type and the PFI channels using a
boolean data type. Each LVDS line is connected
to an OSERDES or ISERDES block that serializes
or deserializes, respectively, the signal by a
factor of eight by default. During acquisition
or generation, the PXIe-6569 reads or writes
eight bits of data per channel to or from the
IDELAY or ODELAY blocks, which allow for per-
channel data delay up to 1.25 ns. All OSERDES
and ISERDES blocks are set to double data rate
(DDR) mode.
© National Instruments
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