National Instruments PXIe-6569 Getting Started Manual page 34

CLIP Signal Name
Configuring Clocks
The PXIe-6569 TX/RX Data Clocks can be driven from multiple sources.
The following figures show the different clock sources available on both the Basic
and the SERDES CLIPs for all modules.
Figure 12. All In Clock Diagram for Basic CLIP
SampleClk
Si514
Configure
Reference Clock
InternalClk
LMK LMK
ExtClkIn
RxSSClk
(DI40)
Figure 13. All In Clock Diagram for SERDES CLIP
SampleClk
Si514
Configure
Reference Clock
DeviceClk
InternalClk
LMK LMK
ExtClkIn
RxSSClk
Bank 44
(DI0)
RxSSClk
Back 45
(DI40)
RxSSClk
Bank 46
(DI46)
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Direction
TX Clock Selection RX Clk Selection
6569 Configure TX Clocks 6569 Configure RX Clocks
MUX
DeviceClk
TX Clk Selection RX Clk Selection
6569 Configure TX Clocks 6569 Configure RX Clocks
MMCM
RX Clk Selection
6569 Configure RX Clocks
RX Clk Selection
6569 Configure RX Clocks
Data Type
FPGA
RxDataClk
MUX
To LabVIEW
FPGA
RxDataClk (Bank 44)
MUX
To LabVIEW
RxDataClk (Bank 45)
MUX
To LabVIEW
RxDataClk (Bank 46)
MUX
To LabVIEW
PXIe-6569 Getting Started Guide
Description
slip channels to align
them in time.