National Instruments PXIe-6569 Getting Started Manual page 35

Figure 14. All Out Clock Diagram for Basic CLIP
SampleClk
Si514
Configure
Reference Clock
DeviceClk
InternalClk
LMK LMK
ExtClkIn
Figure 15. All Out Clock Diagram for SERDES CLIP
SampleClk
Si514
Configure
Reference Clock
DeviceClk
InternalClk
LMK LMK
ExtClkIn
Figure 16. HIHO Clock Diagram for Basic CLIP
SampleClk
Si514
Configure
Reference Clock
DeviceClk
InternalClk
LMK LMK
ExtClkIn
RxSSClk
(DI13)
Figure 17. HIHO Clock Diagram for SERDES CLIP
SampleClk
Si514
Configure
Reference Clock
DeviceClk
InternalClk
LMK LMK
ExtClkIn
RxSSClk
(DI13)
FPGA
TX Clk Selection
6569 Configure TX Clocks
TxDataClk
MUX
To LabVIEW
FPGA
TX Clk Selection
6569 Configure TX Clocks
MMCM TxDataClk
To LabVIEW
FPGA
TX Clk Selection
6569 Configure TX Clocks
MUX
RX Clk Selection
6569 Configure RX Clocks
FPGA
TX Clk Selection
6569 Configure TX Clocks
MMCM
RX Clk Selection
6569 Configure RX Clocks
PXIe-6569 Getting Started Guide
TxDataClk
To LabVIEW
RxDataClk
MUX
To LabVIEW
TxDataClk
To LabVIEW
RxDataClk
MUX
To LabVIEW
© National Instruments
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