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PXIe-6569 Getting Started Guide
CLIP Signal Name
Direction
Data Type
Description
between 2.5 ps and
15 ps. Refer to
the DS892 - Kintex
UltraScale FPGAs
Data Sheet: DC
and AC Switching
Characteristics
document at
www.xilinx.com
for
additional information.
The FPGA delay is
restricted to the
Align_Delay tap value
as the lower limit and
to 511 delay taps as the
upper limit. Refer to
the UG571 - Ultrascale
Architecture SelectIO
Resources user guide
at
www.xilinx.com
for
additional information
on the Align_Delay
tap value.
The PXIe-6569 CLIP
enforces the upper
delay limit by
preventing any further
delay increments when
the tap delay value
of 511 is reached.
The PXIe-6569 CLIP
also enforces the
lower delay limit by
preventing any further
delay decrements
when the Align_Delay
tap value is reached.
28
ni.com
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