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Socketed CLIP Signals
Each LVDS configuration variant of the PXIe-6569 has a different set of signals you
must use in the socketed CLIP. Some CLIP signals and data types are specific to
the module variant being used. The following table lists the term used in the CLIP
signals to represent each associated module variant.
LVDS Configuration Reference in CLIP
Half-In, Half-Out (HIHO)
All In
All Out
Refer to
Front Panel and Connectors
associated FPGA signal information.
PXIe-6569 Basic Socketed CLIP Signals
CLIP Signal Name
IO Ready
IO Error
SE_Data_Output_Enab
le
SE_Data_Rd
SE_Data_Wr
24
ni.com
for PXIe-6569 connector signals and the
Direction
From CLIP
From CLIP
To CLIP
From CLIP
To CLIP
PXIe-6569 Getting Started Guide
PXIe-6569 Variant
32 LVDS In, 32 LVDS Out
64 LVDS In
64 LVDS Out
Data Type
Boolean
I32
Boolean
Boolean
Boolean
Description
Indicates successful
configuration of the
IO module with the
current clocking mode
settings.
Returns IO module
errors, to be reported
by the driver.
Provides read/write
access to all single-
ended channels.
SE_Data_Output_Enab
le values:
1—Use
■
SE_Data_Wr to
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