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Figure 8. PXIe-6569 with 64 LVDS In, Rows B-A
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FPGA Signal
Connector Signal
B1
aSeGpio(11)
B2
B3
B4
aDiffGpio_p(22)
B5
aDiffGpio_n(22)
B6
aDiffGpio_p(26)
B8
aDiffGpio_n(26)
B9
B10
aDiffGpio_p(24)
B11
aDiffGpio_n(24)
B12
B13
aDiffGpio_p(25)
B14
aDiffGpio_n(25)
B15
B16
aDiffGpio_p(27)
B17
aDiffGpio_n(27)
B18
B19
aDiffGpio_p(31)
B20
aDiffGpio_n(31)
B21
B22
aDiffGpio_p(32)
B23
B24
aDiffGpio_n(32)
B25
aDiffGpio_p(40)
B26
aDiffGpio_n(40)
B27
B28
aDiffGpio_p(36)
B29
aDiffGpio_n(36)
B30
B31
aDiffGpio_p(45)
B32
aDiffGpio_n(45)
B33
B34
aDiffGpio_p(39)
B35
aDiffGpio_n(39)
B36
PXIe-6569 Getting Started Guide
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