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CLIP Signal Name
TX/RX Delay Adjust
Steps
TX/RX Delay Increment To CLIP
Direction
To CLIP
PXIe-6569 Getting Started Guide
Data Type
U16
Boolean
Description
LVDS output data or
acquiring the input
data. This clock can
be sourced from the
Si514 or from the
LMK04832 onboard
clocking ICs. Refer to
Figure
2,
Figure
3, and
Figure 5
for additional
information.
Sets the number of
delay steps to apply
to the corresponding
TX/RX data line. This
delay is applied after
the corresponding
TX/RX Delay Adjust
Strobe is asserted.
The delay can only
be adjusted within
the allowable delay
limits of the FPGA.
Adjusting outside these
limits will not change
the delay on the
FPGA. Refer to the
TX/RX Delay Value Rd
signal description for
additional information.
TX/RX Delay Increment
values:
1—Increments
■
the line delay by
the number of
TX/RX Delay
Adjust Steps
when the TX/RX
© National Instruments
31
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