National Instruments PXIe-6569 Getting Started Manual page 21

NI Example Finder FlexRIO Example

Show All FlexRIO with Integrated IO Hardware.vi Queries and displays a set of hardware

Vivado Export Getting Started Ultrascale.lvproj

Read-Write Calibration Data.vi

FPGA Carrier Block Diagram

Configuration, GPIO

GPIO

Module Clocking

Synchronization

Reference

Clock

PXIe-6569 I/O Block Diagram

+1.8 V

Power Supplies

+12 V

Flash

FPGA

DRAM

Bank 0

Bank 1

PXIe-6569 Getting Started Guide

Description

properties from all FlexRIO with Integrated I/O

devices in a chassis.

Demonstrates how to export your LabVIEW

FPGA project into Vivado in order to develop

your FPGA design in the Vivado ADE.

Demonstrates how to read and write calibration

data and metadata into the storage space of

FlexRIO with Integrated I/O devices.

+12 V, +3.3 V

Bus Interface

DStarB, DStarC

PXI Triggers

PXIe_CLK100

PXI_CLK10

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