4.13
I/O Connector D (J1103)
The signals on I/O connector D can be used for user applications and/or for connecting an MMC interface
to the SDIO pins. The MMC signals are activated by setting the CFG A 3 switch. Refer to Section 6.3 for
details.
Warning!
Some of the I/O pins on this connector are routed directly to the FPGA/SoC device. Use only VCC_IO
voltages compliant with the equipped FPGA/SoC device; any other voltage may damage the mounted
Mars FPGA/SoC module, as well as other devices on the Mars EB1 base board.
4.14
Battery Holder (J901)
The battery holder and battery are not mounted in the standard configuration of the Mars EB1 base board.
The battery on the Mars EB1 base board is used for buffering the real-time clock on the connected Mars
FPGA/SoC module. If required, a 3 V lithium battery (CR1220) can be used.
Alternatively, the VCC_BAT_IN power signal can be driven via pin 6 of connector J1101. Refer to Section 4.16
for details.
Type
BC501SM
Table 12: J901 - Battery Holder Type
Warning!
There is a danger of explosion if the battery is replaced incorrectly - only replace the battery with the
same or equivalent type recommended by Enclustra.
Used batteries should be disposed of according to the manufacturer's instructions.
4.15
FPGA JTAG Connector (J1100)
The FPGA JTAG connector allows accessing the JTAG port of the mounted Mars FPGA/SoC module. The
signals on this connector are protected against ESD. Series termination resistors are equipped between the
module signals and the JTAG header.
D-0000-307-001
Manufacturer
Memory Protection Devices
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Version 06, 22.07.2021
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