I 2 C Interface - Silicon Laboratories I2C Manual

Si5338
2
5. I C Interface
Configuration and operation of the Si5338 is controlled
by reading and writing to the RAM space using the I
interface. The device operates in slave mode with 7-bit
addressing and can
(100 kbps) or Fast-Mode (400 kbps) and supports burst
data transfer with auto address increments.
2
The I C bus consists of a bidirectional serial data line
(SDA) and a serial clock input (SCL) as shown in
Figure 21. Both the SDA and SCL pins must be
connected to the VDD supply via an external pull-up as
2
recommended by the I C specification.
V
DD
I2C_LSB
0/1
SCL
2
I C Bus
SDA
2
Figure 21. I C and Control Signals
The 7-bit device (slave) address of the Si5338 consists
of a 6-bit fixed address plus a user-selectable LSB bit as
shown in Figure 22. The LSB bit is selectable using the
optional I2C_LSB pin which is available as an ordering
option for applications that require more than one
2
Si5338 on a single I C bus. Devices without the
I2C_LSB pin option have a fixed 7-bit address of 70h
(111 0000) as shown in Figure 22. Other custom I
addresses are also possible. See Table 17 for details on
device ordering information with the optional I2C_LSB
pin.
6 5 4
Slave Address
1 1 1 0 0 0 0/1
(with I2C_LSB Option)
6 5 4
Slave Address
1 1 1 0 0 0
(without I2C_LSB Option)
Figure 22. Si5338 I
Data is transferred MSB first in 8-bit words as specified
2
by the I C specification. A write command consists of a
7-bit device (slave) address + a write bit, an 8-bit
register address, and 8 bits of data as shown in
Figure 23. A write burst operation is also shown where
every additional data word is written using an auto-
incremented address.
30
operate in Standard-Mode
OEB/PINC/FINC
I2C_LSB/PDEC/FDEC
Control
3 2 1 0
I2C_LSB pin
3 2 1 0
0
2
C Slave Address
Write Operation – Single Byte
S Slv Addr [6:0] 0 A Reg Addr [7:0]
2
C
Write Operation - Burst (Auto Address Increment)
S Slv Addr [6:0] 0 A Reg Addr [7:0]
From slave to master
From master to slave
Figure 23. I
A read operation is performed in two stages. A data
write is used to set the register address, then a data
read is performed to retrieve the data from the set
address. A read burst operation is also supported. This
is shown in Figure 24.
Read Operation – Single Byte
S Slv Addr [6:0] 0 A Reg Addr [7:0]
S Slv Addr [6:0] 1 A Data [7:0]
Read Operation - Burst (Auto Address Increment)
S Slv Addr [6:0] 0 A Reg Addr [7:0]
2
C
S Slv Addr [6:0] 1 A Data [7:0] A
From slave to master
From master to slave
Figure 24. I
AC and dc electrical specifications for the SCL and SDA
pins are shown in Table 15. The timing specifications
and timing diagram for the I
2
the I C-Bus Standard. SDA timeout is supported for
compatibility with SMBus interfaces.
2
The I C bus can be operated at a bus voltage of 1.71 to
3.63 V and is 3.3 V tolerant. If a bus voltage of less than
2.5 V is used, register 27[7] = 1 must be written to
maintain compatibility with the I
Rev. 1.2
A Data [7:0] A P
A Data [7:0] A Data [7:0]
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
2
C Write Operation
A P
N P
A P
Data [7:0] N P
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
2
C Read Operation
2
C bus are compatible with
2
C bus standard.
A P