Page 1 EFM8 Universal Bee Family EFM8UB3 Reference Manual The EFM8UB3, part of the Universal Bee family of MCUs, is a multi-purpose line of 8-bit microcontrollers with USB feature set in KEY FEATURES small packages. • Pipelined 8-bit C8051 core with 48 MHz maximum operating frequency These devices offer high value by integrating an innovative energy-smart USB peripheral •...
Page 2: Table Of Contents
Table of Contents 1. System Overview ......13 1.1 Introduction .......13 1.2 Power .
Page 3 5.2 Unique Identifier ......45 5.3 Device Identification Registers......45 5.3.1 DEVICEID: Device Identification.
Page 4 8.3.3 HFOSC1 48 MHz Internal Oscillator .....72 8.3.4 LFOSC0 80 kHz Internal Oscillator ..... .72 8.3.5 External Clock.
Page 5 11.3 Functional Description ......95 11.3.1 Port I/O Modes of Operation ..... . .95 11.3.2 Analog and Digital Functions .
Page 6 12.3.12 Window Comparator ......134 12.3.13 Temperature Sensor ......136 12.4 ADC0 Control Registers .
Page 7 14.4.1 CLEN0: Configurable Logic Enable 0 ....170 14.4.2 CLIE0: Configurable Logic Interrupt Enable 0 ....171 14.4.3 CLIF0: Configurable Logic Interrupt Flag 0 .
Page 8 16.4.1 PCA0CN0: PCA Control ......201 16.4.2 PCA0MD: PCA Mode ......202 16.4.3 PCA0PWM: PCA PWM Configuration .
Page 9 18.4 SMB0 Control Registers ......248 18.4.1 SMB0CF: SMBus 0 Configuration ..... 248 18.4.2 SMB0TC: SMBus 0 Timing and Pin Control .
Page 10 19.4.29 TMR5L: Timer 5 Low Byte ..... . . 288 19.4.30 TMR5H: Timer 5 High Byte ..... . 2 89 19.4.31 TMR5CN0: Timer 5 Control 0 .
Page 11 21.3.13 Low Energy Mode ......321 21.3.14 Charger Detect Function ..... . .321 21.4 USB0 Control Registers .
Page 12: Vbus Control
23.3 Pin Sharing ......358 23.4 C2 Interface Registers ......359 23.4.1 C2ADD: C2 Address .
Page 13: System Overview
EFM8UB3 Reference Manual System Overview 1. System Overview 1.1 Introduction CIP-51 8051 Controller Port I/O Configuration Core Debug / Programming Hardware Digital Peripherals 40 KB ISP Flash Program Memory UART1 C2CK/RSTb Reset Timers 0, Power-On 256 Byte SRAM 1, 2, 3, 4, 5 Reset Port 0 P0.n...
Page 14: Power
EFM8UB3 Reference Manual System Overview 1.2 Power Control over the device power consumption can be achieved by enabling/disabling individual peripherals as needed. Each analog pe- ripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little power when they are not in use.
Page 15: Clocking
EFM8UB3 Reference Manual System Overview 1.4 Clocking The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system clock comes up running from the 24.5 MHz oscillator divided by 8. The clock control system offers the following features: •...
Page 16 EFM8UB3 Reference Manual System Overview Timers (Timer 0, Timer 1, Timer 2, Timer 3, Timer 4, and Timer 5) Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time inter- vals, count external events and generate periodic interrupt requests.
Page 17: Communications And Other Digital Peripherals
EFM8UB3 Reference Manual System Overview 1.6 Communications and Other Digital Peripherals Universal Serial Bus (USB0) The USB0 peripheral provides a full-speed USB 2.0 compliant device controller and PHY with additional Low Energy USB features. The device supports both full-speed (12MBit/s) and low speed (1.5MBit/s) operation, and includes a dedicated USB oscillator with clock re- covery mechanism for crystal-free operation.
Page 18: Basic Data Transfer
EFM8UB3 Reference Manual System Overview System Management Bus / I2C (SMB0) The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica- tion, version 1.1, and compatible with the I C serial bus. The SMBus module includes the following features: •...
Page 19: Analog
EFM8UB3 Reference Manual System Overview 1.7 Analog 12-Bit Analog-to-Digital Converter (ADC0) The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated track-and hold and a program- mable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to measure different signals using the analog multiplexer.
Page 20: Reset Sources
EFM8UB3 Reference Manual System Overview 1.8 Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • The core halts program execution. • Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset. •...
Page 21: Bootloader
EFM8UB3 Reference Manual System Overview 1.10 Bootloader All devices come pre-programmed with a USB bootloader. This bootloader resides in the code security page and last pages of code flash; it can be erased if it is not needed. The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the boot- loader in the system.
Page 22 EFM8UB3 Reference Manual System Overview Table 1.3. Summary of Pins for Bootload Mode Entry Device Package Pin for Bootload Mode Entry QFN24 P2.0 / C2D QSOP24 P2.0 / C2D QFN20 P2.0 / C2D silabs.com | Building a more connected world. Rev.
Page 23: Memory
EFM8UB3 Reference Manual Memory 2. Memory 2.1 Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types.
Page 24 EFM8UB3 Reference Manual Memory Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also ac- cessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07.
Page 25: Memory Map
EFM8UB3 Reference Manual Memory 2.4 Memory Map 0xFFFF 0xFFFF Memory Lock Read-Only 0xFFFE 64 Bytes 0xFFC0 Read-Only 64 Bytes 0xFFD0 Reserved 0xFFCF 128-bit UUID 0xFFC0 0xFBFF Lock Byte 0xFBFE Bootloader Signature Byte 0xFBFD Security Page 512 Bytes 0xFA00 Bootloader Vector Reserved 0x9DFF 0x9A00...
Page 26 EFM8UB3 Reference Manual Memory On-Chip RAM Accessed with MOV Instructions as Indicated 0xFF Upper 128 Bytes Special Function Registers (Indirect Access) (Direct Access) 0x80 0x7F Lower 128 Bytes RAM (Direct or Indirect Access) 0x30 0x2F Bit-Addressable 0x20 0x1F General-Purpose Register Banks 0x00 Figure 2.2.
Page 27: Xram Control Registers
EFM8UB3 Reference Manual Memory 2.5 XRAM Control Registers 2.5.1 EMI0CN: External Memory Interface Control Name Reserved PGSEL Access Reset SFR Page = ALL; SFR Address: 0xE7 Name Reset Access Description Reserved Must write reset value. PGSEL XRAM Page Select. The XRAM Page Select field provides the high byte of the 16-bit data memory address when using 8-bit MOVX commands, effectively selecting a 256-byte page of RAM.
Page 28: Special Function Registers
EFM8UB3 Reference Manual Special Function Registers 3. Special Function Registers 3.1 Special Function Register Access The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementa- tion as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU.
Page 29 EFM8UB3 Reference Manual Special Function Registers Interrupts and the SFR Page Stack When an interrupt occurs, the current SFRPAGE is pushed onto an SFR page stack to preserve the current context of SFRPAGE. Upon execution of the RETI instruction, the SFRPAGE register is automatically restored to the SFR page that was in use prior to the interrupt.
Page 30: Special Function Register Memory Map
EFM8UB3 Reference Manual Special Function Registers 3.2 Special Function Register Memory Map Table 3.2. Special Function Registers by Address Address SFR Page Address SFR Page (*bit-address- 0x00 0x10 0x20 (*bit-address- 0x00 0x10 0x20 able) able) 0x80* 0xC0* SMB0CN0 TMR5CN0 SMB0CN0 0x81 0xC1 SMB0CF...
Page 31: Faddr: Usb0 Function Address
EFM8UB3 Reference Manual Special Function Registers Address SFR Page Address SFR Page (*bit-address- 0x00 0x10 0x20 (*bit-address- 0x00 0x10 0x20 able) able) 0xA0* 0xE0* 0xA1 SPI0CFG SPI0CFG 0xE1 XBR0 XBR0 0xA2 SPI0CKR TMR4RLL SPI0CKR 0xE2 XBR1 XBR1 0xA3 SPI0DAT TMR4RLH SPI0DAT 0xE3 XBR2...
Page 32 EFM8UB3 Reference Manual Special Function Registers Address SFR Page Address SFR Page (*bit-address- 0x00 0x10 0x20 (*bit-address- 0x00 0x10 0x20 able) able) 0xBF CMP1CN0 USB0CDSTA 0xFF VDM0CN TMR4CN1 Table 3.3. Special Function Registers by Name Register Address SFR Pages Description 0xE0 Accumulator ADC0AC...
Page 33 EFM8UB3 Reference Manual Special Function Registers Register Address SFR Pages Description CLU3CF 0xCA 0x20 Configurable Logic Unit 3 Configuration CLU3FN 0xC7 0x20 Configurable Logic Unit 3 Function Select CLU3MX 0x92 0x20 Configurable Logic Unit 3 Multiplexer CMP0CN0 0x9B 0x00, 0x10 Comparator 0 Control 0 CMP0CN1 0x99...
Page 34 EFM8UB3 Reference Manual Special Function Registers Register Address SFR Pages Description LFO0CN 0xB1 0x00, 0x10 Low Frequency Oscillator Control 0x80 Port 0 Pin Latch P0MASK 0xFE 0x00, 0x20 Port 0 Mask P0MAT 0xFD 0x00, 0x20 Port 0 Match P0MDIN 0xF1 0x00, 0x20 Port 0 Input Mode P0MDOUT...
Page 35 EFM8UB3 Reference Manual Special Function Registers Register Address SFR Pages Description PFE0CN 0xC1 0x10 Prefetch Engine Control PRTDRV 0xF6 0x00, 0x20 Port Drive Strength PSCTL 0x8F Program Store Control PSTAT0 0xAD 0x10 Power Status 0xD0 Program Status Word REF0CN 0xD1 0x00, 0x10 Voltage Reference Control REG0CN...
Page 36 EFM8UB3 Reference Manual Special Function Registers Register Address SFR Pages Description SPI0PCF 0xDF 0x20 SPI0 Pin Configuration TCON 0x88 Timer 0/1 Control 0x8C Timer 0 High Byte 0x8D Timer 1 High Byte 0x8A Timer 0 Low Byte 0x8B Timer 1 Low Byte TMOD 0x89 Timer 0/1 Mode...
Page 37: Sfr Access Control Registers
EFM8UB3 Reference Manual Special Function Registers Register Address SFR Pages Description USB0AEC 0xB2 0x20 USB0 Advanced Energy Control USB0CDCF 0xB6 0x20 USB0 Charger Detect Configuration USB0CDCN 0xBE 0x20 USB0 Charger Detect Control USB0CDSTA 0xBF 0x20 USB0 Charger Detect Status USB0CF 0xB5 0x20 USB0 Configuration...
Page 38: Sfrpgcn: Sfr
EFM8UB3 Reference Manual Special Function Registers 3.3.2 SFRPGCN: SFR Page Control Name Reserved SFRPGIDX Reserved SFRPGEN Access Reset SFR Page = 0x10; SFR Address: 0xCF Name Reset Access Description Reserved Must write reset value. SFRPGIDX SFR Page Stack Index. This field can be used to access the SFRPAGE values stored in the SFR page stack. It selects the level of the stack firm- ware can access when reading the SFRSTACK register.
Page 39: Flash Memory
EFM8UB3 Reference Manual Flash Memory 4. Flash Memory 4.1 Introduction On-chip, re-programmable flash memory is included for program code and non-volatile data storage. The flash memory is organized in 512-byte pages. It can be erased and written through the C2 interface or from firmware by overloading the MOVX instruction. Any indi- vidual byte in flash memory must only be written once between page erase operations.
Page 40: Functional Description
EFM8UB3 Reference Manual Flash Memory 4.3 Functional Description 4.3.1 Security Options The CIP-51 provides security options to protect the flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register PSCTL) bits protect the flash memory from accidental modification by software.
Page 41: Programming The Flash Memory
EFM8UB3 Reference Manual Flash Memory Table 4.3. Flash Security Summary—C2 Permissions Target Area for Read / Write / Erase Permissions from C2 interface Any Unlocked Page [R] [W] [E] Any Locked Page Device Erase Only Read-Only Area Reserved Area None [R] = Read permitted [W] = Write permitted [E] = Erase permitted...
Page 42: Flash Write And Erase Precautions
EFM8UB3 Reference Manual Flash Memory 4.3.2.3 Flash Byte Write Procedure The flash memory is written by firmware using the MOVX write instruction with the address and data byte to be programmed provided as normal operands in DPTR and A. Before writing to flash memory using MOVX, flash write operations must be enabled by setting the PSWE bit in the PSCTL register to logic 1 (this directs the MOVX writes to target flash memory) and writing the flash key codes in sequence to the FLKEY register.
Page 43: Flash Control Registers
EFM8UB3 Reference Manual Flash Memory PSWE Maintenance • Reduce the number of places in code where the PSWE bit (in register PSCTL) is set to a 1. There should be exactly one routine in code that sets PSWE to a 1 to write flash bytes and one routine in code that sets PSWE and PSEE both to a 1 to erase flash pages. •...
Page 44: Flkey: Flash Lock And Key
EFM8UB3 Reference Manual Flash Memory 4.4.2 FLKEY: Flash Lock and Key Name FLKEY Access Reset 0x00 SFR Page = ALL; SFR Address: 0xB7 Name Reset Access Description FLKEY 0x00 Flash Lock and Key. Write: This register provides a lock and key function for flash erasures and writes. Flash writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register.
Page 45: Device Identification
EFM8UB3 Reference Manual Device Identification 5. Device Identification 5.1 Device Identification The SFR map includes registers that may be used to identify the device family (DEVICEID), derivative (DERIVID), and revision (RE- VID). These SFRs can be read by firmware at runtime to determine the capabilities of the MCU that is executing code. This allows the same firmware image to run on MCUs with different memory sizes and peripherals, and dynamically change functionality to suit the capabilities of that MCU.
Page 46: Derivid: Derivative Identification
EFM8UB3 Reference Manual Device Identification 5.3.2 DERIVID: Derivative Identification Name DERIVID Access Reset Varies SFR Page = 0x0; SFR Address: 0xAD Name Reset Access Description DERIVID Varies Derivative ID. This read-only register returns the 8-bit derivative ID, which can be used by firmware to identify which device in the product family the code is executing on.
Page 47: Interrupts
EFM8UB3 Reference Manual Interrupts 6. Interrupts 6.1 Introduction The MCU core includes an extended interrupt system supporting multiple interrupt sources and priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Interrupt sources may have one or more associated interrupt-pending flag(s) located in an SFR local to the associated peripheral.
Page 48: Interrupt Latency
EFM8UB3 Reference Manual Interrupts 6.2.2 Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority deco- ded on every system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR.
Page 49: Interrupt Summary
EFM8UB3 Reference Manual Interrupts 6.2.3 Interrupt Summary Table 6.2. Interrupt Priority Table Interrupt Source Vector Priority Primary Enable Auxiliary Enable(s) Pending Flag(s) Reset 0x0000 External Interrupt 0 0x0003 IE_EX0 TCON_IE0 Timer 0 Overflow 0x000B IE_ET0 TCON_TF0 External Interrupt 1 0x0013 IE_EX1 TCON_IE1 Timer 1 Overflow...
Page 50 EFM8UB3 Reference Manual Interrupts Interrupt Source Vector Priority Primary Enable Auxiliary Enable(s) Pending Flag(s) USB0 Events 0x007B EIE2_EUSB0 CMIE_RSTINTE CMINT_RSTINT CMIE_RSUINTE CMINT_RSUINT CMIE_SOFE CMINT_SOF CMIE_SUSINTE CMINT_SUSINT IN1IE_EP0E IN1INT_EP0 IN1IE_IN1E IN1INT_IN1 IN1IE_IN2E IN1INT_IN2 IN1IE_IN3E IN1INT_IN3 OUT1IE_OUT1E OUT1INT_OUT1 OUT1IE_OUT2E OUT1INT_OUT2 OUT1IE_OUT3E OUT1INT_OUT3 VBUS / USB Charge De- 0x0083 EIE2_EVBUS...
Page 51: Interrupt Control Registers
EFM8UB3 Reference Manual Interrupts 6.3 Interrupt Control Registers 6.3.1 IE: Interrupt Enable Name ESPI0 Access Reset SFR Page = ALL; SFR Address: 0xA8 (bit-addressable) Name Reset Access Description All Interrupts Enable. Globally enables/disables all interrupts and overrides individual interrupt mask settings. Value Name Description...
Page 52 EFM8UB3 Reference Manual Interrupts Name Reset Access Description External Interrupt 1 Enable. This bit sets the masking of External Interrupt 1. Value Name Description DISABLED Disable external interrupt 1. ENABLED Enable interrupt requests generated by the INT1 input. Timer 0 Interrupt Enable. This bit sets the masking of the Timer 0 interrupt.
Page 53: Ip: Interrupt Priority
EFM8UB3 Reference Manual Interrupts 6.3.2 IP: Interrupt Priority Name Reserved PSPI0 Access Reset SFR Page = ALL; SFR Address: 0xB8 (bit-addressable) Name Reset Access Description Reserved Must write reset value. PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control LSB. This bit sets the LSB of the priority field for the SPI0 interrupt. Timer 2 Interrupt Priority Control LSB.
Page 54: Iph: Interrupt Priority High
EFM8UB3 Reference Manual Interrupts 6.3.3 IPH: Interrupt Priority High Name Reserved PHSPI0 PHT2 PHS1 PHT1 PHX1 PHT0 PHX0 Access Reset SFR Page = 0x10; SFR Address: 0xF2 Name Reset Access Description Reserved Must write reset value. PHSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control MSB. This bit sets the MSB of the priority field for the SPI0 interrupt.
Page 55: Eie1: Extended Interrupt Enable 1
EFM8UB3 Reference Manual Interrupts 6.3.4 EIE1: Extended Interrupt Enable 1 Name ECP1 ECP0 EPCA0 EADC0 EWADC0 EMAT ESMB0 Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xE6 Name Reset Access Description Timer 3 Interrupt Enable. This bit sets the masking of the Timer 3 interrupt. Value Name Description...
Page 56 EFM8UB3 Reference Manual Interrupts Name Reset Access Description EWADC0 ADC0 Window Comparison Interrupt Enable. This bit sets the masking of ADC0 Window Comparison interrupt. Value Name Description DISABLED Disable ADC0 Window Comparison interrupt. ENABLED Enable interrupt requests generated by ADC0 Window Compare flag (ADWINT).
Page 57: Eip1: Extended Interrupt Priority 1 Low
EFM8UB3 Reference Manual Interrupts 6.3.5 EIP1: Extended Interrupt Priority 1 Low Name PCP1 PCP0 PPCA0 PADC0 PWADC0 PMAT PSMB0 Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xF3 Name Reset Access Description Timer 3 Interrupt Priority Control LSB. This bit sets the LSB of the priority field for the Timer 3 interrupt. PCP1 Comparator1 (CP1) Interrupt Priority Control LSB.
Page 58: Eip1H: Extended Interrupt Priority 1 High
EFM8UB3 Reference Manual Interrupts 6.3.6 EIP1H: Extended Interrupt Priority 1 High Name PHT3 PHCP1 PHCP0 PHPCA0 PHADC0 PHWADC0 PHMAT PHSMB0 Access Reset SFR Page = 0x10; SFR Address: 0xF5 Name Reset Access Description PHT3 Timer 3 Interrupt Priority Control MSB. This bit sets the MSB of the priority field for the Timer 3 interrupt.
Page 59: Eie2: Extended Interrupt Enable 2
EFM8UB3 Reference Manual Interrupts 6.3.7 EIE2: Extended Interrupt Enable 2 Name Reserved ECL0 Reserved EVBUS EUSB0 Access Reset SFR Page = 0x10; SFR Address: 0xCE Name Reset Access Description Reserved Must write reset value. ECL0 Configurable Logic (CL0) Interrupt Enable. This bit sets the masking of the CL0 interrupts.
Page 60: Eip2: Extended Interrupt Priority 2
EFM8UB3 Reference Manual Interrupts 6.3.8 EIP2: Extended Interrupt Priority 2 Name Reserved PCL0 Reserved PVBUS PUSB0 Access Reset SFR Page = 0x10; SFR Address: 0xF4 Name Reset Access Description Reserved Must write reset value. PCL0 Configurable Logic (CL0) Interrupt Priority Control LSB. This bit sets the LSB of the priority field for the CL0 interrupt.
Page 61: Eip2H: Extended Interrupt Priority 2 High
EFM8UB3 Reference Manual Interrupts 6.3.9 EIP2H: Extended Interrupt Priority 2 High Name Reserved PHCL0 Reserved PHT5 PHT4 PHVBUS PHUSB0 Access Reset SFR Page = 0x10; SFR Address: 0xF6 Name Reset Access Description Reserved Must write reset value. PHCL0 Configurable Logic (CL0) Interrupt Priority Control MSB. This bit sets the MSB of the priority field for the CL0 interrupt.
Page 62: Power Management And Internal Regulators
EFM8UB3 Reference Manual Power Management and Internal Regulators 7. Power Management and Internal Regulators 7.1 Introduction Control over the device power consumption can be achieved by enabling/disabling individual peripherals as needed. Each analog pe- ripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little power when they are not in use.
Page 63: Features
EFM8UB3 Reference Manual Power Management and Internal Regulators Power Mode Details Mode Entry Wake-Up Sources Stop • All internal power nets shut down 1. Clear STOPCF bit in Any reset source REG0CN • 5V regulator remains active (if enabled) 2. Set STOP bit in •...
Page 64: Idle Mode
EFM8UB3 Reference Manual Power Management and Internal Regulators 7.3 Idle Mode In idle mode, CPU core execution is halted while any enabled peripherals and clocks remain active. Power consumption in idle mode is dependent upon the system clock frequency and any active peripherals. Setting the IDLE bit in the PCON0 register causes the hardware to halt the CPU and enter idle mode as soon as the instruction that sets the bit completes execution.
Page 65: Snooze Mode
EFM8UB3 Reference Manual Power Management and Internal Regulators 7.6 Snooze Mode Snooze mode is entered by setting the SNOOZE bit while operating from the internal 24.5 MHz oscillator (HFOSC0). Upon entry into snooze mode, the hardware halts both of the high-frequency internal oscillators and goes into a low power state as soon as the instruc- tion that sets the bit completes execution.
Page 66: Power Management Control Registers
EFM8UB3 Reference Manual Power Management and Internal Regulators 7.9 Power Management Control Registers 7.9.1 PCON0: Power Control Name STOP IDLE Access Reset SFR Page = ALL; SFR Address: 0x87 Name Reset Access Description General Purpose Flag 5. This flag is a general purpose flag for use under firmware control. General Purpose Flag 4.
Page 67: Pcon1: Power Control 1
EFM8UB3 Reference Manual Power Management and Internal Regulators 7.9.2 PCON1: Power Control 1 Name SNOOZE SUSPEND Reserved Access Reset 0x00 SFR Page = ALL; SFR Address: 0xE4 Name Reset Access Description SNOOZE Snooze Mode Select. Setting this bit will place the device in snooze mode. High speed oscillators will be halted the SYSCLK signal will be gated off, and the internal regulator will be placed in a low power state.
Page 68: Pstat0: Power Status
EFM8UB3 Reference Manual Power Management and Internal Regulators 7.9.3 PSTAT0: Power Status Name Reserved CL0WK USB0RWK SPI0WK TMR4WK PMATWK CPT0WK Access Reset SFR Page = 0x10; SFR Address: 0xAD Name Reset Access Description Reserved Must write reset value. CL0WK CL0 Wake-up Event. Value Name Description...
Page 69: Reg0Cn: Voltage Regulator 0 Control
EFM8UB3 Reference Manual Power Management and Internal Regulators 7.9.4 REG0CN: Voltage Regulator 0 Control Name Reserved STOPCF Reserved Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xC9 Name Reset Access Description Reserved Must write reset value. STOPCF Stop and Shutdown Mode Configuration. This bit configures the regulator's behavior when the device enters stop mode.
Page 70: Reg1Cn: Voltage Regulator 1 Control
EFM8UB3 Reference Manual Power Management and Internal Regulators 7.9.5 REG1CN: Voltage Regulator 1 Control Name REG1ENB Reserved BIASENB SUSEN Reserved Access Reset SFR Page = 0x20; SFR Address: 0xC6 Name Reset Access Description REG1ENB Voltage Regulator 1 Disable. This bit may be used to disable the 5V regulator if an external regulator is used to power VDD. VREGIN should be tied to VDD in any system that disables this regulator.
Page 71: Clocking And Oscillators
EFM8UB3 Reference Manual Clocking and Oscillators 8. Clocking and Oscillators 8.1 Introduction The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system clock comes up running from the 24.5 MHz oscillator divided by 8. Clock Control 48 MHz Oscillator (HFOSC1)
Page 72: Hfosc0 24.5 Mhz Internal Oscillator
EFM8UB3 Reference Manual Clocking and Oscillators 8.3.2 HFOSC0 24.5 MHz Internal Oscillator HFOSC0 is a programmable internal high-frequency oscillator that is factory-calibrated to 24.5 MHz. The oscillator is automatically ena- bled when it is requested. The oscillator period can be adjusted via the HFO0CAL register to obtain other frequencies. Note: Changing the HFO0CAL register value from its default value may degrade the frequency stability of the oscillator across temper- ature and supply voltage.
Page 73: Clocking And Oscillator Control Registers
EFM8UB3 Reference Manual Clocking and Oscillators 8.4 Clocking and Oscillator Control Registers 8.4.1 CLKSEL: Clock Select Name DIVRDY CLKDIV Reserved CLKSL Access Reset SFR Page = ALL; SFR Address: 0xA9 Name Reset Access Description DIVRDY Clock Divider Ready. Indicates when the clock has propagated through the divider with the current CLKDIV setting. Value Name Description...
Page 74: Hfo0Cal: High Frequency Oscillator 0 Calibration
EFM8UB3 Reference Manual Clocking and Oscillators Name Reset Access Description HFOSC1_DIV_1P5 Clock derived from the Internal High Frequency Oscillator 1, pre-scaled by 1.5. This device family has restrictions when switching to clock sources that are greater than 25 MHz. SYSCLK must be running at a fre- quency of 24 MHz or greater before switching the CLKSL field to HFOSC1.
Page 75: Hfocn: High Frequency Oscillator Control
EFM8UB3 Reference Manual Clocking and Oscillators 8.4.4 HFOCN: High Frequency Oscillator Control Name HFO1EN Reserved HFO0EN Reserved Access Reset SFR Page = 0x10; SFR Address: 0xEF Name Reset Access Description HFO1EN HFOSC1 Oscillator Enable. Value Name Description DISABLED Disable High Frequency Oscillator 1 (HFOSC1 will still turn on if re- quested by any block in the device or selected as the SYSCLK source).
Page 76: Lfo0Cn: Low Frequency Oscillator Control
EFM8UB3 Reference Manual Clocking and Oscillators 8.4.5 LFO0CN: Low Frequency Oscillator Control Name OSCLEN OSCLRDY OSCLF OSCLD Access Reset Varies SFR Page = 0x0, 0x10; SFR Address: 0xB1 Name Reset Access Description OSCLEN Internal L-F Oscillator Enable. This bit enables the internal low-frequency oscillator. Note that the low-frequency oscillator is automatically enabled when the watchdog timer is active.
Page 77: Reset Sources And Power Supply Monitor
EFM8UB3 Reference Manual Reset Sources and Power Supply Monitor 9. Reset Sources and Power Supply Monitor 9.1 Introduction Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: •...
Page 78: Functional Description
EFM8UB3 Reference Manual Reset Sources and Power Supply Monitor 9.3 Functional Description 9.3.1 Device Reset Upon entering a reset state from any source, the following events occur: • The processor core halts program execution. • Special Function Registers (SFRs) are initialized to their defined reset values. •...
Page 79: Power-On Reset
EFM8UB3 Reference Manual Reset Sources and Power Supply Monitor 9.3.2 Power-On Reset During power-up, the POR circuit fires. When POR fires, the device is held in a reset state and the RSTb pin is driven low until the supply voltage settles above V .
Page 80: Supply Monitor Reset
EFM8UB3 Reference Manual Reset Sources and Power Supply Monitor 9.3.3 Supply Monitor Reset The supply monitor senses the voltage on the device's supply pin and can generate a reset if the supply drops below the corresponding threshold. This monitor is enabled and enabled as a reset source after initial power-on to protect the device until the supply is an ade- quate and stable voltage.
Page 81: Comparator (Cmp0) Reset
EFM8UB3 Reference Manual Reset Sources and Power Supply Monitor 9.3.6 Comparator (CMP0) Reset Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag. Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into the reset state.
Page 82: Reset Sources And Supply Monitor Control Registers
EFM8UB3 Reference Manual Reset Sources and Power Supply Monitor 9.4 Reset Sources and Supply Monitor Control Registers 9.4.1 RSTSRC: Reset Source Name USBRSF FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Access Reset Varies Varies Varies Varies Varies Varies Varies Varies SFR Page = 0x0;...
Page 83: Vdm0Cn: Supply Monitor Control
EFM8UB3 Reference Manual Reset Sources and Power Supply Monitor 9.4.2 VDM0CN: Supply Monitor Control Name VDMEN VDDSTAT Reserved Access Reset Varies Varies Varies SFR Page = 0x0; SFR Address: 0xFF Name Reset Access Description VDMEN Varies Supply Monitor Enable. This bit turns the supply monitor circuit on/off. The supply monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC.
Page 84: Microcontroller Core
EFM8UB3 Reference Manual CIP-51 Microcontroller Core 10. CIP-51 Microcontroller Core 10.1 Introduction The CIP-51 microcontroller core is a high-speed, pipelined, 8-bit core utilizing the standard MCS-51™ instruction set. Any standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051.
Page 85: Features
EFM8UB3 Reference Manual CIP-51 Microcontroller Core Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. The CIP-51 core executes 76 of its 109 instructions in one or two clock cycles, with no instructions taking more than eight clock cycles. The table below shows the distribution of instructions vs.
Page 86: Instruction Set
EFM8UB3 Reference Manual CIP-51 Microcontroller Core 10.3.3 Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 de- velopment tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51™...
Page 87 EFM8UB3 Reference Manual CIP-51 Microcontroller Core Mnemonic Description Bytes Clock Cycles prefetch off prefetch on ANL A, Rn AND Register to A ANL A, direct AND direct byte to A ANL A, @Ri AND indirect RAM to A ANL A, #data AND immediate to A ANL direct, A AND A to direct byte...
Page 88 EFM8UB3 Reference Manual CIP-51 Microcontroller Core Mnemonic Description Bytes Clock Cycles prefetch off prefetch on MOV direct, @Ri Move indirect RAM to direct byte MOV direct, #data Move immediate to direct byte MOV @Ri, A Move A to indirect RAM MOV @Ri, direct Move direct byte to indirect RAM MOV @Ri, #data...
Page 89 EFM8UB3 Reference Manual CIP-51 Microcontroller Core Mnemonic Description Bytes Clock Cycles prefetch off prefetch on Program Branching ACALL addr11 Absolute subroutine call LCALL addr16 Long subroutine call Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address)
Page 90: Cpu Core Registers
EFM8UB3 Reference Manual CIP-51 Microcontroller Core 10.4 CPU Core Registers 10.4.1 DPL: Data Pointer Low Name Access Reset 0x00 SFR Page = ALL; SFR Address: 0x82 Name Reset Access Description 0x00 Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed flash memory or XRAM. 10.4.2 DPH: Data Pointer High Name Access...
Page 91: Acc: Accumulator
EFM8UB3 Reference Manual CIP-51 Microcontroller Core 10.4.4 ACC: Accumulator Name Access Reset 0x00 SFR Page = ALL; SFR Address: 0xE0 (bit-addressable) Name Reset Access Description 0x00 Accumulator. This register is the accumulator for arithmetic operations. 10.4.5 B: B Register Name Access Reset 0x00...
Page 92: Psw: Program Status Word
EFM8UB3 Reference Manual CIP-51 Microcontroller Core 10.4.6 PSW: Program Status Word Name PARITY Access Reset SFR Page = ALL; SFR Address: 0xD0 (bit-addressable) Name Reset Access Description Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations.
Page 93: Pfe0Cn: Prefetch Engine Control
EFM8UB3 Reference Manual CIP-51 Microcontroller Core 10.4.7 PFE0CN: Prefetch Engine Control Name Reserved FLRT Reserved Access Reset SFR Page = 0x10; SFR Address: 0xC1 Name Reset Access Description Reserved Must write reset value. FLRT Flash Read Timing. This field should be programmed to the smallest allowed value, according to the system clock speed. When transitioning to a faster clock speed, program FLRT before changing the clock.
Page 94: Port I/O, Crossbar, External Interrupts, And Port Match
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11. Port I/O, Crossbar, External Interrupts, and Port Match 11.1 Introduction Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.6 can be defined as gen- eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an analog function.
Page 95: Functional Description
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.3 Functional Description 11.3.1 Port I/O Modes of Operation Port pins are configured by firmware as digital or analog I/O using the special function registers. Port I/O initialization consists of the following general steps: 1.
Page 96: Analog And Digital Functions
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match Configuring Port Pins For Digital Modes Any pins to be used by digital peripherals or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Page 97 EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.3.2.2 Port I/O Digital Assignments The following table displays the potential mapping of port I/O to each digital function. Table 11.2. Port I/O Assignment for Digital Functions Digital Function Potentially Assignable Port Pins SFR(s) Used For Assignment UART1, SPI0, SMB0, CP0, CP0A, CP1,...
Page 98: Priority Crossbar Decoder
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.3.3 Priority Crossbar Decoder The priority crossbar decoder assigns a priority to each I/O function, starting at the top with UART0. The XBRn registers are used to control which crossbar resources are assigned to physical I/O port pins. When a digital resource is selected, the least-significant unassigned port pin is assigned to that resource (excluding UART0, which is always assigned to dedicated pins).
Page 99 EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.3.3.1 Crossbar Functional Map The figure below shows all of the potential peripheral-to-pin assignments available to the crossbar. Note that this does not mean any peripheral can always be assigned to the highlighted pins. The actual pin assignments are determined by the priority of the enabled peripherals.
Page 100: Int0 And Int1
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.3.4 INT0 and INT1 Two direct-pin digital interrupt sources (INT0 and INT1) are included, which can be routed to port 0 pins. Additional I/O interrupts are available through the port match function. As is the case on a standard 8051 architecture, certain controls for these two interrupt sour- ces are available in the Timer0/1 registers.
Page 101: Port I/O Control Registers
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4 Port I/O Control Registers 11.4.1 XBR0: Port I/O Crossbar 0 Name SYSCKE CP1AE CP1E CP0AE CP0E SMB0E SPI0E URT1EL Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xE1 Name Reset Access...
Page 102 EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match Name Reset Access Description Value Name Description DISABLED SPI I/O unavailable at Port pins. ENABLED SPI I/O routed to Port pins. The SPI can be assigned either 3 or 4 GPIO pins.
Page 103: Xbr1: Port I/O Crossbar 1
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.2 XBR1: Port I/O Crossbar 1 Name Reserved ECIE PCA0ME Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xE2 Name Reset Access Description Reserved Must write reset value. T2 Enable.
Page 104: Xbr2: Port I/O Crossbar 2
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.3 XBR2: Port I/O Crossbar 2 Name WEAKPUD XBARE Reserved URT1CTSE URT1RTSE URT1E Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xE3 Name Reset Access Description WEAKPUD Port I/O Weak Pullup Disable. Value Name Description...
Page 105: Prtdrv: Port Drive Strength
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.4 PRTDRV: Port Drive Strength Name Reserved P2DRV P1DRV P0DRV Access Reset 0x00 SFR Page = 0x0, 0x20; SFR Address: 0xF6 Name Reset Access Description Reserved Must write reset value. P2DRV Port 2 Drive Strength.
Page 106: P0Mask: Port 0 Mask
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.5 P0MASK: Port 0 Mask Name Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xFE Name Reset Access Description Port 0 Bit 7 Mask Value. Value Name Description IGNORED P0.7 pin logic value is ignored and will not cause a port mismatch event.
Page 107: P0Mat: Port 0 Match
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.6 P0MAT: Port 0 Match Name Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xFD Name Reset Access Description Port 0 Bit 7 Match Value. Value Name Description P0.7 pin logic value is compared with logic LOW.
Page 108: P0: Port 0 Pin Latch
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.7 P0: Port 0 Pin Latch Name Access Reset SFR Page = ALL; SFR Address: 0x80 (bit-addressable) Name Reset Access Description Port 0 Bit 7 Latch. Value Name Description P0.7 is low.
Page 109: P0Mdin: Port 0 Input Mode
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.8 P0MDIN: Port 0 Input Mode Name Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xF1 Name Reset Access Description Port 0 Bit 7 Input Mode. Value Name Description ANALOG P0.7 pin is configured for analog mode.
Page 110: P0Mdout: Port 0 Output Mode
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.9 P0MDOUT: Port 0 Output Mode Name Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xA4 Name Reset Access Description Port 0 Bit 7 Output Mode. Value Name Description OPEN_DRAIN P0.7 output is open-drain.
Page 111: P0Skip: Port 0 Skip
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.10 P0SKIP: Port 0 Skip Name Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xD4 Name Reset Access Description Port 0 Bit 7 Skip. Value Name Description NOT_SKIPPED P0.7 pin is not skipped by the crossbar.
Page 112: P1Mask: Port 1 Mask
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.11 P1MASK: Port 1 Mask Name Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xEE Name Reset Access Description Port 1 Bit 7 Mask Value. Value Name Description IGNORED P1.7 pin logic value is ignored and will not cause a port mismatch event.
Page 113: P1Mat: Port 1 Match
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.12 P1MAT: Port 1 Match Name Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xED Name Reset Access Description Port 1 Bit 7 Match Value. Value Name Description P1.7 pin logic value is compared with logic LOW.
Page 114: P1: Port 1 Pin Latch
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.13 P1: Port 1 Pin Latch Name Access Reset SFR Page = ALL; SFR Address: 0x90 (bit-addressable) Name Reset Access Description Port 1 Bit 7 Latch. Value Name Description P1.7 is low.
Page 115: P1Mdin: Port 1 Input Mode
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.14 P1MDIN: Port 1 Input Mode Name Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xF2 Name Reset Access Description Port 1 Bit 7 Input Mode. Value Name Description ANALOG P1.7 pin is configured for analog mode.
Page 116: P1Mdout: Port 1 Output Mode
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.15 P1MDOUT: Port 1 Output Mode Name Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xA5 Name Reset Access Description Port 1 Bit 7 Output Mode. Value Name Description OPEN_DRAIN P1.7 output is open-drain.
Page 117: P1Skip: Port 1 Skip
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.16 P1SKIP: Port 1 Skip Name Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xD5 Name Reset Access Description Port 1 Bit 7 Skip. Value Name Description NOT_SKIPPED P1.7 pin is not skipped by the crossbar.
Page 118: P2Mask: Port 2 Mask
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.17 P2MASK: Port 2 Mask Name Reserved Access Reset 0x00 SFR Page = 0x20; SFR Address: 0xFC Name Reset Access Description Reserved Must write reset value. Port 2 Bit 1 Mask Value. Value Name Description...
Page 119: P2: Port 2 Pin Latch
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.19 P2: Port 2 Pin Latch Name Reserved Access Reset 0x00 SFR Page = ALL; SFR Address: 0xA0 (bit-addressable) Name Reset Access Description Reserved Must write reset value. Port 2 Bit 1 Latch. Value Name Description...
Page 120: P2Mdout: Port 2 Output Mode
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.4.21 P2MDOUT: Port 2 Output Mode Name Reserved Access Reset 0x00 SFR Page = 0x0, 0x20; SFR Address: 0xA6 Name Reset Access Description Reserved Must write reset value. Port 2 Bit 1 Output Mode. Value Name Description...
Page 121: Int0 And Int1 Control Registers
EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match 11.5 INT0 and INT1 Control Registers 11.5.1 IT01CF: INT0/INT1 Configuration Name IN1PL IN1SL IN0PL IN0SL Access Reset SFR Page = 0x0, 0x10; SFR Address: 0x85 Name Reset Access Description IN1PL INT1 Polarity.
Page 122 EFM8UB3 Reference Manual Port I/O, Crossbar, External Interrupts, and Port Match Name Reset Access Description P0_3 Select P0.3. P0_4 Select P0.4. P0_5 Select P0.5. P0_6 Select P0.6. P0_7 Select P0.7. silabs.com | Building a more connected world. Rev. 0.2 | 122...
Page 123: Analog-To-Digital Converter (Adc0)
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12. Analog-to-Digital Converter (ADC0) 12.1 Introduction The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated track-and hold and a program- mable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to measure different signals using the analog multiplexer.
Page 124: Features
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.2 Features • Up to 16 external inputs. • Single-ended 12-bit and 10-bit modes. • Supports an output update rate of 200 ksps samples per second in 12-bit mode or 800 ksps samples per second in 10-bit mode. •...
Page 125: Input Selection
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.3.2.4 Ground Reference To prevent ground noise generated by switching digital logic from affecting sensitive analog measurements, a separate analog ground reference option is available. When enabled, the ground reference for the ADC during both the tracking/sampling and the conversion periods is taken from the AGND pin.
Page 126: Gain Setting
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) ADC0MX setting Signal Name Enumeration Name QFN24 Pin QSOP24 Pin QFN20 Pin Name Name Name 10100 - 10111 ADC0.20 - ADC0.23 Reserved Reserved Reserved 11000 ADC0.24 ADC0P24 P2.1 P2.1 P2.1 11001 - 11011 ADC0.25 - ADC0.27 Reserved Reserved Reserved...
Page 127 EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) Settling Time Requirements The absolute minimum tracking time is given in the electrical specifications tables. It may be necessary to track for longer than the mini- mum tracking time specification, depending on the application. For example, if the ADC input is presented with a large series impe- dance, it will take longer for the sampling cap to settle on the final value during the tracking phase.
Page 128 EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) Configuring the Tracking Time When burst mode is disabled, the ADTM bit controls the ADC track-and-hold mode. In its default state the ADC input is continuously tracked, except when a conversion is in progress. A conversion will begin immediately when the start-of-conversion trigger occurs. When the ADTM bit is logic 1, each conversion is preceded by a tracking period of 4 SAR clocks (after the start-of-conversion signal) for any internal conversion trigger source.
Page 129: Burst Mode
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) Convert Start ADTM = 1 Powered Power-Up Powered Power-Up T C.. ADEN = 0 Down and Track Down and Track ADTM = 0 Powered Power-Up Powered Power-Up T C T C T C T C.. ADEN = 0 Down and Track...
Page 130: 12-Bit Mode
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.3.9 12-Bit Mode When configured for 12-bit conversions, the ADC performs four 10-bit conversions using four different reference voltages and combines the results into a single 12-bit value. Unlike simple averaging techniques, this method provides true 12-bit resolution of ac or dc input signals without depending on noise to provide dithering.
Page 131: Output Formatting
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.3.10 Output Formatting The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the ADSJST field. When the repeat count is set to 1 in 10-bit mode, conversion codes are represented as 10-bit unsigned integers.
Page 132: Power Considerations
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.3.11 Power Considerations The ADC has several power-saving features which can help the user optimize power consumption according to the needs of the appli- cation. The most efficient way to use the ADC for slower sample rates is by using burst mode. Burst mode dynamically controls power to the ADC and (if used) the internal voltage reference.
Page 133 EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) Required Reference Source Mode Configuration SAR Clock Speed Other Register Field Set- Throughput tings 125-180 ksps Always-On + Burst Mode 12.25 MHz ADC0PWR = 0x40 (ADEN = 1 ADBMEN = 1) (ADSC = 1) ADC0TK = 0x3A ADRPT = 1 0-125 ksps...
Page 134: Window Comparator
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.3.12 Window Comparator The ADC's programmable window detector continuously compares the ADC output registers to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt driven system, saving code space and CPU bandwidth while delivering faster system response times.
Page 135 EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) Comparison Register Settings Output Code (ADC0H:L) ADWINT Effects ADC0GTH:L = 0x0040 0x0040 ADWINT Not Affected 0x003F 0x0000 Table 12.10. ADC Window Comparator Example (Outside the 0x0040 to 0x0080 range) Comparison Register Settings Output Code (ADC0H:L) ADWINT Effects 0x03FF ADWINT = 1...
Page 136: Temperature Sensor
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.3.13 Temperature Sensor An on-chip analog temperature sensor is available to the ADC multiplexer input. To use the ADC to measure the temperature sensor, the ADC mux channel should select the temperature sensor. The temperature sensor transfer function is shown in Figure 12.6 Temper- ature Sensor Transfer Function on page 136.
Page 137: Adc0Cn0: Adc0 Control 0
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.4 ADC0 Control Registers 12.4.1 ADC0CN0: ADC0 Control 0 Name ADEN ADBMEN ADINT ADBUSY ADWINT Reserved Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xE8 (bit-addressable) Name Reset Access Description ADEN ADC Enable. Value Name Description...
Page 138: Adc0Cn1: Adc0 Control 1
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.4.2 ADC0CN1: ADC0 Control 1 Name ADCM Reserved ADCMBE Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xB2 Name Reset Access Description ADCM Start of Conversion Mode Select. Specifies the ADC0 start of conversion source. All remaining bit combinations are reserved. Value Name Description...
Page 139: Adc0Cf: Adc0 Configuration
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.4.3 ADC0CF: ADC0 Configuration Name ADSC AD8BE ADTM ADGN Access Reset 0x1F SFR Page = 0x0, 0x10; SFR Address: 0xBC Name Reset Access Description ADSC 0x1F SAR Clock Divider. This field sets the ADC clock divider value. It should be configured to be as close to the maximum SAR clock speed as the datasheet will allow.
Page 140: Adc0Ac: Adc0 Accumulator Configuration
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.4.4 ADC0AC: ADC0 Accumulator Configuration Name AD12BE ADAE ADSJST ADRPT Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xB3 Name Reset Access Description AD12BE 12-Bit Mode Enable. Enables 12-bit mode. In 12-bit mode, the ADC throughput is reduced by a factor of 4. Value Name Description...
Page 141 EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) Name Reset Access Description ACC_32 Perform and Accumulate 32 conversions (8 conversions in 12-bit mode). ACC_64 Perform and Accumulate 64 conversions (16 conversions in 12-bit mode). silabs.com | Building a more connected world. Rev. 0.2 | 141...
Page 142: Adc0Pwr: Adc0 Power Control
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.4.5 ADC0PWR: ADC0 Power Control Name ADBIAS ADMXLP ADLPM ADPWR Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xDF Name Reset Access Description ADBIAS Bias Power Select. This field can be used to adjust the ADC's power consumption based on the conversion speed. Higher bias currents allow for faster conversion times.
Page 143: Adc0Tk: Adc0 Burst Mode Track Time
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.4.6 ADC0TK: ADC0 Burst Mode Track Time Name AD12SM Reserved ADTK Access Reset 0x1E SFR Page = 0x0, 0x10; SFR Address: 0xB9 Name Reset Access Description AD12SM 12-Bit Sampling Mode. This bit controls the way that the ADC samples the input when in 12-bit mode. When the ADC is configured for multiple 12- bit conversions in burst mode, the AD12SM bit should be cleared to 0.
Page 144: Adc0L: Adc0 Data Word Low Byte
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.4.8 ADC0L: ADC0 Data Word Low Byte Name ADC0L Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0xBD Name Reset Access Description ADC0L 0x00 Data Word Low Byte. When read, this register returns the least significant byte of the 16-bit ADC0 accumulator, formatted according to the set- tings in ADSJST.
Page 145: Adc0Lth: Adc0 Less-Than High Byte
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.4.11 ADC0LTH: ADC0 Less-Than High Byte Name ADC0LTH Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0xC6 Name Reset Access Description ADC0LTH 0x00 Less-Than High Byte. Most significant byte of the 16-bit less-than window compare register. 12.4.12 ADC0LTL: ADC0 Less-Than Low Byte Name ADC0LTL...
Page 146: Ref0Cn: Voltage Reference Control
EFM8UB3 Reference Manual Analog-to-Digital Converter (ADC0) 12.4.14 REF0CN: Voltage Reference Control Name IREFLVL Reserved GNDSL REFSL TEMPE Reserved Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xD1 Name Reset Access Description IREFLVL Internal Voltage Reference Level. Sets the voltage level for the internal reference source. Value Name Description...
Page 147: Comparators (Cmp0 And Cmp1)
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13. Comparators (CMP0 and CMP1) 13.1 Introduction Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and negative inputs.
Page 148: Functional Description
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13.3 Functional Description 13.3.1 Response Time and Supply Current Response time is the amount of time delay between a change at the comparator inputs and the comparator's reaction at the output. The comparator response time may be configured in software via the CPMD field in the CMPnMD register. Selecting a longer response time reduces the comparator supply current, while shorter response times require more supply current.
Page 149 EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13.3.3.1 Multiplexer Channel Selection Table 13.1. CMP0 Positive Input Multiplexer Channels CMXP Setting in Signal Name Enumeration Name QFN24 Pin QSOP24 Pin QFN20 Pin Register Name Name Name CMP0MX 0000 CMP0P.0 CMP0P0 P0.0 P0.0 P0.0 0001...
Page 150 EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) CMXP Setting in Signal Name Enumeration Name QFN24 Pin QSOP24 Pin QFN20 Pin Register Name Name Name CMP1MX 0010 CMP1P.2 CMP1P2 P1.2 P1.2 P1.2 0011 CMP1P.3 CMP1P3 P1.3 P1.3 Reserved 0100 CMP1P.4 CMP1P4 P1.4 P1.4 Reserved...
Page 151 EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13.3.3.2 Reference DAC The comparator module includes a dedicated reference DAC, which can be inserted between the selected mux channel and the com- parator on either the positive or negative inputs. The INSL field in the CMPnMD register determines the connections between the selec- ted mux inputs, the reference DAC, and the comparator inputs.
Page 152 EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) CMXP CMPnP.0 CMPnP.1 CMPnP.2 CMPnP.3 CMPn+ CMPnP.x CMPn- Figure 13.4. Negative Input Ground Connection When INSL is configured to use the reference DAC on the negative channel, the positive comparator mux selection is directly connec- ted to the positive comparator input.
Page 153: Output Routing
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) CMXP CMPnP.0 CMPnP.1 CMPnP.2 CMPnP.3 Full Scale Reference CMPnP.x CMPn+ DACLVL CMXN CMPn- CMPnN.0 CMPnN.1 CMPnN.2 CMPnN.3 CMPnN.x Figure 13.6. Positive Input DAC Connection 13.3.4 Output Routing The comparator’s synchronous and asynchronous outputs can optionally be routed to port I/O pins through the port I/O crossbar. The output of either comparator may be configured to generate a system interrupt on rising, falling, or both edges.
Page 154 EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13.3.4.2 Output Inhibit The comparator module includes a feature to inhibit output changes whenever the PCA's CEX2 channel is logic low. This can be used to prevent undersirable glitches during known noise events, such as power FET switching. The CPINH bit in register CMPnCN1 enables this option.
Page 155: Cmp0 Control Registers
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13.4 CMP0 Control Registers 13.4.1 CMP0CN0: Comparator 0 Control 0 Name CPEN CPOUT CPRIF CPFIF CPHYP CPHYN Access Reset SFR Page = 0x0, 0x10; SFR Address: 0x9B Name Reset Access Description CPEN Comparator Enable. Value Name Description...
Page 156 EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) Name Reset Access Description CPHYN Comparator Negative Hysteresis Control. Value Name Description DISABLED Negative Hysteresis disabled. ENABLED_MODE1 Negative Hysteresis = Hysteresis 1. ENABLED_MODE2 Negative Hysteresis = Hysteresis 2. ENABLED_MODE3 Negative Hysteresis = Hysteresis 3 (Maximum). silabs.com | Building a more connected world.
Page 157: Cmp0Md: Comparator 0 Mode
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13.4.2 CMP0MD: Comparator 0 Mode Name CPLOUT CPINV CPRIE CPFIE INSL CPMD Access Reset SFR Page = 0x0, 0x10; SFR Address: 0x9D Name Reset Access Description CPLOUT Comparator Latched Output Flag. This bit represents the comparator output value at the most recent PCA counter overflow. Value Name Description...
Page 158: Cmp0Mx: Comparator 0 Multiplexer Selection
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) Name Reset Access Description CMXP_DAC Connect the CMP- input to the internal DAC output, and CMP+ is se- lected by CMXP. The internal DAC uses the signal specified by CMXN as its full-scale reference. CPMD Comparator Mode Select.
Page 159: Cmp0Cn1: Comparator 0 Control 1
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13.4.4 CMP0CN1: Comparator 0 Control 1 Name CPINH Reserved DACLVL Access Reset 0x00 SFR Page = 0x10; SFR Address: 0x99 Name Reset Access Description CPINH Output Inhibit. This bit is used to inhibit the comparator output during CEX2 low times. Value Name Description...
Page 160: Cmp1 Control Registers
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13.5 CMP1 Control Registers 13.5.1 CMP1CN0: Comparator 1 Control 0 Name CPEN CPOUT CPRIF CPFIF CPHYP CPHYN Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xBF Name Reset Access Description CPEN Comparator Enable. Value Name Description...
Page 161 EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) Name Reset Access Description CPHYN Comparator Negative Hysteresis Control. Value Name Description DISABLED Negative Hysteresis disabled. ENABLED_MODE1 Negative Hysteresis = Hysteresis 1. ENABLED_MODE2 Negative Hysteresis = Hysteresis 2. ENABLED_MODE3 Negative Hysteresis = Hysteresis 3 (Maximum). silabs.com | Building a more connected world.
Page 162: Cmp1Md: Comparator 1 Mode
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13.5.2 CMP1MD: Comparator 1 Mode Name CPLOUT CPINV CPRIE CPFIE INSL CPMD Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xAB Name Reset Access Description CPLOUT Comparator Latched Output Flag. This bit represents the comparator output value at the most recent PCA counter overflow. Value Name Description...
Page 163: Cmp1Mx: Comparator 1 Multiplexer Selection
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) Name Reset Access Description CMXP_DAC Connect the CMP- input to the internal DAC output, and CMP+ is se- lected by CMXP. The internal DAC uses the signal specified by CMXN as its full-scale reference. CPMD Comparator Mode Select.
Page 164: Cmp1Cn1: Comparator 1 Control 1
EFM8UB3 Reference Manual Comparators (CMP0 and CMP1) 13.5.4 CMP1CN1: Comparator 1 Control 1 Name CPINH Reserved DACLVL Access Reset 0x00 SFR Page = 0x10; SFR Address: 0xAC Name Reset Access Description CPINH Output Inhibit. This bit is used to inhibit the comparator output during CEX2 low times. Value Name Description...
Page 165: Configurable Logic Units (Clu0, Clu1, Clu2, Clu3)
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14. Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.1 Introduction The configurable logic (CL) module provides multiple blocks of user-programmed digital logic that operates without CPU intervention. It consists of four dedicated independent configurable logic units (CLUs) which support user programmable asynchronous and synchro- nous boolean logic operations.
Page 166: Features
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) CLUn Input Mux A Carry to CLU[n+1] External Pins Look Timer Overflow Pulses Table PCA Channels (LUT) CnEN CLU Asynch Outputs CMP Asynch Outputs CLUnOUT Input Mux B CnOUTa CnEN Asynchronous Output (to other CLUs) CnEN...
Page 167: Functional Description
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.3 Functional Description 14.3.1 Configuration Sequence Firmware should configure the function select, mux inputs and output functionality before enabling individual CLUs. CLU initialization consists of the following general steps: 1. Select the A and B inputs to the LUT in CLUnMX 2.
Page 168 EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.3.2.1 CLU Multiplexer Input Selection Table 14.1. CLUnA Input Selection CLUnMX.MXA CLU0A CLU1A CLU2A CLU3A C0OUTa C0OUTa C0OUTa C0OUTa C1OUTa C1OUTa C1OUTa C1OUTa C2OUTa C2OUTa C2OUTa C2OUTa C3OUTa C3OUTa C3OUTa C3OUTa Timer2 Overflow Timer3 Overflow...
Page 169: Output Configuration
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.3.3 Output Configuration Each CLU presents an asynchronous and a synchronous (synchronized to SYSCLK) output to the system. The synchronous output may be read by firmware at any time by reading the CLOUT0 register. CLU outputs may be derived directly from the LUT, or from a latched D-type flip-flop output, as controlled by the OUTSEL bit in CLUnCF.
Page 170: Configurable Logic Control Registers
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4 Configurable Logic Control Registers 14.4.1 CLEN0: Configurable Logic Enable 0 Name Reserved C3EN C2EN C1EN C0EN Access Reset SFR Page = 0x20; SFR Address: 0xCB Name Reset Access Description Reserved Must write reset value.
Page 171: Clie0: Configurable Logic Interrupt Enable 0
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.2 CLIE0: Configurable Logic Interrupt Enable 0 Name C3RIE C3FIE C2RIE C2FIE C1RIE C1FIE C0RIE C0FIE Access Reset SFR Page = 0x20; SFR Address: 0xCD Name Reset Access Description C3RIE CLU3 Rising Edge Interrupt Enable.
Page 172: Clif0: Configurable Logic Interrupt Flag 0
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.3 CLIF0: Configurable Logic Interrupt Flag 0 Name C3RIF C3FIF C2RIF C2FIF C1RIF C1FIF C0RIF C0FIF Access Reset SFR Page = 0x20; SFR Address: 0xE8 (bit-addressable) Name Reset Access Description C3RIF CLU3 Rising Edge Flag.
Page 173: Clout0: Configurable Logic Output 0
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.4 CLOUT0: Configurable Logic Output 0 Name Reserved C3OUT C2OUT C1OUT C0OUT Access Reset SFR Page = 0x20; SFR Address: 0xD9 Name Reset Access Description Reserved Must write reset value. C3OUT CLU3 Output State.
Page 174: Clu0Fn: Configurable Logic Unit 0 Function Select
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.6 CLU0FN: Configurable Logic Unit 0 Function Select Name FNSEL Access Reset 0x00 SFR Page = 0x20; SFR Address: 0xAD Name Reset Access Description FNSEL 0x00 CLU Look-Up-Table function select. Function select for the CLU0 LUT.
Page 175: Clu0Cf: Configurable Logic Unit 0 Configuration
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.7 CLU0CF: Configurable Logic Unit 0 Configuration Name OUTSEL Reserved CLKINV CLKSEL Access Reset SFR Page = 0x20; SFR Address: 0xB1 Name Reset Access Description OUTSEL CLU Output Select. Value Name Description D_FF...
Page 176: Clu1Mx: Configurable Logic Unit 1 Multiplexer
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.8 CLU1MX: Configurable Logic Unit 1 Multiplexer Name Access Reset SFR Page = 0x20; SFR Address: 0x85 Name Reset Access Description CLU1 A Input Multiplexer Selection. Selects the A input to CLU1. CLU1 B Input Multiplexer Selection.
Page 177: Clu1Cf: Configurable Logic Unit 1 Configuration
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.10 CLU1CF: Configurable Logic Unit 1 Configuration Name OUTSEL Reserved CLKINV CLKSEL Access Reset SFR Page = 0x20; SFR Address: 0xBB Name Reset Access Description OUTSEL CLU Output Select. Value Name Description D_FF...
Page 178: Clu2Mx: Configurable Logic Unit 2 Multiplexer
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.11 CLU2MX: Configurable Logic Unit 2 Multiplexer Name Access Reset SFR Page = 0x20; SFR Address: 0x91 Name Reset Access Description CLU2 A Input Multiplexer Selection. Selects the A input to CLU2. CLU2 B Input Multiplexer Selection.
Page 179: Clu2Cf: Configurable Logic Unit 2 Configuration
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.13 CLU2CF: Configurable Logic Unit 2 Configuration Name OUTSEL Reserved CLKINV CLKSEL Access Reset SFR Page = 0x20; SFR Address: 0xBD Name Reset Access Description OUTSEL CLU Output Select. Value Name Description D_FF...
Page 180: Clu3Mx: Configurable Logic Unit 3 Multiplexer
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.14 CLU3MX: Configurable Logic Unit 3 Multiplexer Name Access Reset SFR Page = 0x20; SFR Address: 0x92 Name Reset Access Description CLU3 A Input Multiplexer Selection. Selects the A input to CLU3. CLU3 B Input Multiplexer Selection.
Page 181: Clu3Cf: Configurable Logic Unit 3 Configuration
EFM8UB3 Reference Manual Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) 14.4.16 CLU3CF: Configurable Logic Unit 3 Configuration Name OUTSEL Reserved CLKINV CLKSEL Access Reset SFR Page = 0x20; SFR Address: 0xCA Name Reset Access Description OUTSEL CLU Output Select. Value Name Description D_FF...
Page 182: Cyclic Redundancy Check (Crc0)
EFM8UB3 Reference Manual Cyclic Redundancy Check (CRC0) 15. Cyclic Redundancy Check (CRC0) 15.1 Introduction The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the flash contents of the device.
Page 183: Functional Description
EFM8UB3 Reference Manual Cyclic Redundancy Check (CRC0) 15.3 Functional Description 15.3.1 16-bit CRC Algorithm The CRC unit generates a 16-bit CRC result equivalent to the following algorithm: 1. XOR the input with the most-significant bits of the current CRC result. If this is the first iteration of the CRC unit, the current CRC result will be the set initial value (0x0000 or 0xFFFF).
Page 184: Using The Crc On A Data Stream
EFM8UB3 Reference Manual Cyclic Redundancy Check (CRC0) 15.3.2 Using the CRC on a Data Stream The CRC module may be used to perform CRC calculations on any data set available to the firmware. To perform a CRC on an arbitra- ry data sream: 1.
Page 185: Crc0 Control Registers
EFM8UB3 Reference Manual Cyclic Redundancy Check (CRC0) 15.4 CRC0 Control Registers 15.4.1 CRC0CN0: CRC0 Control 0 Name Reserved CRCINIT CRCVAL Reserved CRCPNT Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xCE Name Reset Access Description Reserved Must write reset value. CRCINIT CRC Initialization Enable.
Page 186: Crc0Dat: Crc0 Data Output
EFM8UB3 Reference Manual Cyclic Redundancy Check (CRC0) 15.4.3 CRC0DAT: CRC0 Data Output Name CRC0DAT Access Reset 0x00 SFR Page = 0x0, 0x20; SFR Address: 0xDE Name Reset Access Description CRC0DAT 0x00 CRC Data Output. Each read or write performed on CRC0DAT targets the CRC result bits pointed to by the CRC0 Result Pointer (CRCPNT bits in CRC0CN0).
Page 187: Crc0Flip: Crc0 Bit Flip
EFM8UB3 Reference Manual Cyclic Redundancy Check (CRC0) 15.4.6 CRC0FLIP: CRC0 Bit Flip Name CRC0FLIP Access Reset 0x00 SFR Page = 0x0, 0x20; SFR Address: 0xCF Name Reset Access Description CRC0FLIP 0x00 CRC0 Bit Flip. Any byte written to CRC0FLIP is read back in a bit-reversed order, i.e., the written LSB becomes the MSB. For example: If 0xC0 is written to CRC0FLIP, the data read back will be 0x03.
Page 188: Programmable Counter Array (Pca0)
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16. Programmable Counter Array (PCA0) 16.1 Introduction The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare mod- ule for each channel.
Page 189: Features
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.2 Features • 16-bit time base • Programmable clock divisor and clock source selection • Up to three independently-configurable channels • 8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation) •...
Page 190: Interrupt Sources
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.3.2 Interrupt Sources The PCA0 module shares one interrupt vector among all of its modules. There are are several event flags that can be used to generate a PCA0 interrupt. They are as follows: the main PCA counter overflow flag (CF), which is set upon a 16-bit overflow of the PCA0 coun- ter;...
Page 191: Edge-Triggered Capture Mode
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.3.3.1 Output Polarity The output polarity of each PCA channel is individually selectable using the PCA0POL register. By default, all output channels are con- figured to drive the PCA output signals (CEXn) with their internal polarity. When the CEXnPOL bit for a specific channel is set to 1, that channel’s output signal will be inverted at the pin.
Page 192: Software Timer (Compare) Mode
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.3.5 Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN0 is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is enabled.
Page 193: High-Speed Output Mode
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.3.6 High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the capture/compare flag (CCFn) in PCA0CN0 is set to logic 1.
Page 194: Frequency Output Mode
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.3.7 Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/ compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined as follows: CEXn 2 ×...
Page 195 EFM8UB3 Reference Manual Programmable Counter Array (PCA0) Edge Aligned PWM When configured for edge-aligned mode, a module generates an edge transition at two points for every 2 PCA clock cycles, where N is the selected PWM resolution in bits. In edge-aligned mode, these two edges are referred to as the “match” and “overflow” edges. The polarity at the output pin is selectable and can be inverted by setting the appropriate channel bit to 1 in the PCA0POL register.
Page 196 EFM8UB3 Reference Manual Programmable Counter Array (PCA0) PCA0CPn Duty Cycle = Figure 16.8. N-bit Edge-Aligned PWM Duty Cycle With CEXnPOL = 1 (N = PWM resolution) silabs.com | Building a more connected world. Rev. 0.2 | 196...
Page 197 EFM8UB3 Reference Manual Programmable Counter Array (PCA0) Center Aligned PWM When configured for center-aligned mode, a module generates an edge transition at two points for every 2(N+1) PCA clock cycles, where N is the selected PWM resolution in bits. In center-aligned mode, these two edges are referred to as the “up” and “down” edges. The polarity at the output pin is selectable and can be inverted by setting the appropriate channel bit to 1 in the PCA0POL register.
Page 198 EFM8UB3 Reference Manual Programmable Counter Array (PCA0) - PCA0CPn - Duty Cycle = Figure 16.10. N-bit Center-Aligned PWM Duty Cycle With CEXnPOL = 0 (N = PWM resolution) PCA0CPn + Duty Cycle = Figure 16.11. N-bit Center-Aligned PWM Duty Cycle With CEXnPOL = 1 (N = PWM resolution) 16.3.8.1 8 to 11-Bit PWM Modes Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin.
Page 199 EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.3.8.2 16-Bit PWM Mode A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other PWM modes. The entire PCA0CP register is used to determine the duty cycle in 16-bit PWM mode. To output a varying duty cycle, new value writes should be synchronized with the PCA CCFn match flag to ensure seamless updates.
Page 200 EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.3.8.3 Comparator Clear Function In 8/9/10/11/16-bit PWM modes, the comparator clear function utilizes the Comparator0 output synchronized to the system clock to clear CEXn to logic low for the current PWM cycle. This comparator clear function can be enabled for each PWM channel by setting the CPCEn bits to 1 in the PCA0CLR SFR.
Page 201: Pca0 Control Registers
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) CEXn (CPCEn = 0) Comparator0 Output (CPCPOL = 1) CEXn (CPCEn = 1) Figure 16.15. CEXn with CPCEn = 1, CPCPOL = 1 16.4 PCA0 Control Registers 16.4.1 PCA0CN0: PCA Control Name Reserved CCF2 CCF1 CCF0...
Page 202: Pca0Md: Pca Mode
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.2 PCA0MD: PCA Mode Name CIDL Reserved Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xD9 Name Reset Access Description CIDL PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. Value Name Description...
Page 203: Pca0Pwm: Pca Pwm Configuration
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.3 PCA0PWM: PCA PWM Configuration Name ARSEL ECOV COVF Reserved CLSEL Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xF7 Name Reset Access Description ARSEL Auto-Reload Register Select. This bit selects whether to read and write the normal PCA capture/compare registers (PCA0CPn), or the Auto-Reload reg- isters at the same SFR addresses.
Page 204: Pca0Clr: Pca Comparator Clear Control
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.4 PCA0CLR: PCA Comparator Clear Control Name CPCPOL CPSEL Reserved CPCE2 CPCE1 CPCE0 Access Reset SFR Page = 0x0, 0x10; SFR Address: 0x9C Name Reset Access Description CPCPOL Comparator Clear Polarity. Selects the polarity of the comparator result that will clear the PCA channel(s). Value Name Description...
Page 205: Pca0H: Pca Counter/Timer High Byte
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.6 PCA0H: PCA Counter/Timer High Byte Name PCA0H Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0xFA Name Reset Access Description PCA0H 0x00 PCA Counter/Timer High Byte. The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer. Reads of this register will read the con- tents of a "snapshot"...
Page 206: Pca0Cent: Pca Center Alignment Enable
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.8 PCA0CENT: PCA Center Alignment Enable Name Reserved CEX2CEN CEX1CEN CEX0CEN Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0x9E Name Reset Access Description Reserved Must write reset value. CEX2CEN CEX2 Center Alignment Enable. Selects the alignment properties of the CEX2 output channel when operated in any of the PWM modes.
Page 207: Pca0Cpm0: Pca Channel 0 Capture/Compare Mode
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.9 PCA0CPM0: PCA Channel 0 Capture/Compare Mode Name PWM16 ECOM CAPP CAPN ECCF Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xDA Name Reset Access Description PWM16 Channel 0 16-bit Pulse Width Modulation Enable. This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
Page 208: Pca0Cpl0: Pca Channel 0 Capture Module Low Byte
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.10 PCA0CPL0: PCA Channel 0 Capture Module Low Byte Name PCA0CPL0 Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0xFB Name Reset Access Description PCA0CPL0 0x00 PCA Channel 0 Capture Module Low Byte. The PCA0CPL0 register holds the low byte (LSB) of the 16-bit capture module.
Page 209: Pca0Cpm1: Pca Channel 1 Capture/Compare Mode
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.12 PCA0CPM1: PCA Channel 1 Capture/Compare Mode Name PWM16 ECOM CAPP CAPN ECCF Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xDB Name Reset Access Description PWM16 Channel 1 16-bit Pulse Width Modulation Enable. This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
Page 210: Pca0Cpl1: Pca Channel 1 Capture Module Low Byte
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.13 PCA0CPL1: PCA Channel 1 Capture Module Low Byte Name PCA0CPL1 Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0xE9 Name Reset Access Description PCA0CPL1 0x00 PCA Channel 1 Capture Module Low Byte. The PCA0CPL1 register holds the low byte (LSB) of the 16-bit capture module.
Page 211: Pca0Cpm2: Pca Channel 2 Capture/Compare Mode
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.15 PCA0CPM2: PCA Channel 2 Capture/Compare Mode Name PWM16 ECOM CAPP CAPN ECCF Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xDC Name Reset Access Description PWM16 Channel 2 16-bit Pulse Width Modulation Enable. This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
Page 212: Pca0Cpl2: Pca Channel 2 Capture Module Low Byte
EFM8UB3 Reference Manual Programmable Counter Array (PCA0) 16.4.16 PCA0CPL2: PCA Channel 2 Capture Module Low Byte Name PCA0CPL2 Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0xEB Name Reset Access Description PCA0CPL2 0x00 PCA Channel 2 Capture Module Low Byte. The PCA0CPL2 register holds the low byte (LSB) of the 16-bit capture module.
Page 213: Serial Peripheral Interface (Spi0)
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) 17. Serial Peripheral Interface (SPI0) 17.1 Introduction The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers.
Page 214: Functional Description
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) 17.3 Functional Description 17.3.1 Signals The SPI interface consists of up to four signals: MOSI, MISO, SCK, and NSS. Master Out, Slave In (MOSI): The MOSI signal is the data output pin when configured as a master device and the data input pin when configured as a slave.
Page 215: Master Mode Operation
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) Master Device 1 Slave Device MISO MISO MOSI MOSI port pin Master Device 2 MOSI MISO port pin Figure 17.4. Multi-Master Connection Diagram 17.3.1.1 Routing Input Signals Through Configurable Logic All of the SPI signals are routed through the crossbar by default. It is also possible to route the inputs to the SPI from certain CLU outputs, as controlled by the SPI0PCF register.
Page 216: Slave Mode Operation
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) 17.3.3 Slave Mode Operation When the SPI block is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by an external master device controlling the SCK signal. A bit counter in the SPI logic counts SCK edges.
Page 217: Clock Phase And Polarity
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) 17.3.4 Clock Phase and Polarity Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPInCFG register. The CKPHA bit selects one of two clock phases (edge used to latch the data). The CKPOL bit selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity.
Page 218: Using The Spi Fifos
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) (CKPOL=0, CKPHA=1) (CKPOL=1, CKPHA=1) MOSI Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (4-Wire Mode) Figure 17.7.
Page 219 EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) FIFO Data Interface Writing and reading the FIFOs is straightforward, and similar to the procedure outlined in 17.3.5 Basic Data Transfer. All FIFO writes and reads are performed through the SPInDAT register. To write data into the transmit buffer, firmware should first check the status of the TXNF bit.
Page 220 EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) Slave Receiver Timeout When acting as a SPI slave using RFRQ interrupts and with the RXTH field set to a value greater than 0, it is possible for the external master to write too few bytes to the device to immediately generate an interrupt. To avoid leaving lingering bytes in the receive FIFO, the slave receiver timeout feature may be used.
Page 221: Spi Timing Diagrams
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) 17.3.7 SPI Timing Diagrams SCK* MCKH MCKL MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.8. SPI Master Timing (CKPHA = 0) SCK* MCKH MCKL...
Page 222 EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) SCK* MOSI MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.10. SPI Slave Timing (CKPHA = 0) SCK* MOSI MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.11.
Page 223 EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) Table 17.1. SPI Timing Parameters Parameter Description Units Master Mode Timing SCK High Time 1 x T — MCKH SYSCLK SCK Low Time 1 x T — MCKL SYSCLK MISO Valid to SCK Sample Edge —...
Page 224: Spi0 Control Registers
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) 17.4 SPI0 Control Registers 17.4.1 SPI0CFG: SPI0 Configuration Name SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xA1 Name Reset Access Description SPIBSY SPI Busy. This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
Page 225 EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) Name Reset Access Description Value Name Description NOT_EMPTY The RX FIFO contains data. EMPTY The RX FIFO is empty. silabs.com | Building a more connected world. Rev. 0.2 | 225...
Page 226: Spi0Cn0: Spi0 Control
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) 17.4.2 SPI0CN0: SPI0 Control Name SPIF WCOL MODF RXOVRN NSSMD TXNF SPIEN Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xF8 (bit-addressable) Name Reset Access Description SPIF SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If SPIF interrupts are enabled with the SPIFEN bit, an interrupt will be generated.
Page 227: Spi0Ckr: Spi0 Clock Rate
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) Name Reset Access Description ENABLED Enable the SPI module. 17.4.3 SPI0CKR: SPI0 Clock Rate Name SPI0CKR Access Reset 0x00 SFR Page = 0x0, 0x20; SFR Address: 0xA2 Name Reset Access Description SPI0CKR 0x00 SPI0 Clock Rate.
Page 228: Spi0Fcn0: Spi0 Fifo Control
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) 17.4.5 SPI0FCN0: SPI0 FIFO Control 0 Name TFRQE TFLSH TXTH RFRQE RFLSH RXTH Access Reset SFR Page = 0x20; SFR Address: 0x9A Name Reset Access Description TFRQE Write Request Interrupt Enable. When set to 1, a SPI0 interrupt will be generated any time TFRQ is logic 1. Value Name Description...
Page 229 EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) 17.4.6 SPI0FCN1: SPI0 FIFO Control 1 Name TFRQ THPOL TXHOLD SPIFEN RFRQ Reserved RXTOE RXFIFOE Access Reset SFR Page = 0x20; SFR Address: 0x9B Name Reset Access Description TFRQ Transmit FIFO Request. Set to 1 by hardware when the number of bytes in the TX FIFO is less than or equal to the TX FIFO threshold (TXTH). Value Name Description...
Page 230: Spi0Fct: Spi0 Fifo Count
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) Name Reset Access Description RXTOE Receive Timeout Enable. This bit enables the RX FIFO timeout function. If the RX FIFO is not empty, the number of bytes in the FIFO is not enough to generate a Receive FIFO request, and the timeout is reached, a SPI0 interrupt will be generated.
Page 231: Spi0Pcf: Spi0 Pin Configuration
EFM8UB3 Reference Manual Serial Peripheral Interface (SPI0) 17.4.8 SPI0PCF: SPI0 Pin Configuration Name SCKSEL Reserved MISEL Reserved SISEL Access Reset SFR Page = 0x20; SFR Address: 0xDF Name Reset Access Description SCKSEL Slave Clock Input Select. This field selects the source of the SCK input signal in slave mode. Value Name Description...
Page 232: System Management Bus / I2C (Smb0)
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18. System Management Bus / I2C (SMB0) 18.1 Introduction The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica- tion, version 1.1, and compatible with the I C serial bus.
Page 233: Smbus Protocol
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18.3.2 SMBus Protocol The SMBus specification allows any recessive voltage between 3.0 and 5.0 V; different devices on the bus may operate at different voltage levels. However, the maximum voltage on any port pin must conform to the electrical characteristics specifications. The bi-direc- tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit.
Page 234 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) SLA6 SLA5-0 D6-0 START Slave Address + R/W Data Byte NACK STOP Figure 18.3. SMBus Transaction Transmitter vs. Receiver On the SMBus communications interface, a device is the “transmitter” when it is sending an address or data byte to another device on the bus.
Page 235: Configuring The Smbus Module
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18.3.3 Configuring the SMBus Module The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent features: •...
Page 236 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus master and/or slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit.
Page 237 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) SMBus Timing Control The SDD field in the SMBus Timing Control register is used to delay the recognition of the falling edge of the SDA signal. This feature should be applied in cases where a data bit transition occurs close to the SCL falling edge that may cause a false START detection when there is a significant mismatch between the impedance or capacitance on the SDA and SCL lines.
Page 238 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) Hardware ACK Generation When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK generation is enabled. As a re- ceiver, the value currently specified by the ACK bit will be automatically sent on the bus during the ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on the last ACK cycle.
Page 239 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) Hardware Slave Address Recognition The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an ACK without software inter- vention. Automatic slave address recognition is enabled by setting the EHACK bit in register SMB0ADM to 1. This will enable both auto- matic slave address recognition and automatic hardware ACK generation for received bytes (as a master or slave).
Page 240: Operational Modes
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18.3.4 Operational Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an arbitration or generates a STOP.
Page 241 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) Master Write Sequence During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit.
Page 242 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) Idle Set the STA bit. Interrupt STA sent. 1. Clear the STA and STO flags. 2. Write SMB0DAT with the slave address and R/W bit set to 1. 3. Clear the interrupt flag (SI). Interrupt Send ACK?
Page 243 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) Master Read Sequence During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit.
Page 244 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) Idle Set the STA bit. Interrupt STA sent. 1. Clear the STA and STO flags. 2. Write SMB0DAT with the slave address and R/W bit set to 1. 3. Clear the interrupt flag (SI). Interrupt Send ACK?
Page 245 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) Slave Write Sequence During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received.
Page 246 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) Idle Interrupt 1. Clear STA. 2. Read Address + R/W from SMB0DAT. Read Write Read / Write? 1. Set ACK. 1. Write next data to SMB0DAT. 2. Clear SI. 2. Clear SI. Interrupt Interrupt 1.
Page 247 EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) Slave Read Sequence During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the ad- dress byte, and a transmitter during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received.
Page 248: Smb0 Control Registers
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18.4 SMB0 Control Registers 18.4.1 SMB0CF: SMBus 0 Configuration Name ENSMB BUSY EXTHOLD SMBTOE SMBFTE SMBCS Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xC1 Name Reset Access Description ENSMB SMBus Enable.
Page 249: Smb0Tc: Smbus 0 Timing And Pin Control
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18.4.2 SMB0TC: SMBus 0 Timing and Pin Control Name SWAP Reserved DLYEXT Reserved Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xAC Name Reset Access Description SWAP SMBus Swap Pins. This bit swaps the order of the SMBus pins on the crossbar.
Page 250: Smb0Cn0: Smbus 0 Control
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18.4.3 SMB0CN0: SMBus 0 Control Name MASTER TXMODE ACKRQ ARBLOST Access Reset SFR Page = 0x0, 0x20; SFR Address: 0xC0 (bit-addressable) Name Reset Access Description MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. Value Name Description...
Page 251: Smb0Adr: Smbus 0 Slave Address
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) Name Reset Access Description SMBus Acknowledge. When read as a master, the ACK bit indicates whether an ACK (1) or NACK (0) is received during the most recent byte transfer. As a slave, this bit should be written to send an ACK (1) or NACK (0) to a master request. Note that the logic level of the ACK bit on the SMBus interface is inverted from the logic of the register ACK bit.
Page 252: Smb0Adm: Smbus 0 Slave Address Mask
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18.4.5 SMB0ADM: SMBus 0 Slave Address Mask Name SLVM EHACK Access Reset 0x7F SFR Page = 0x0, 0x20; SFR Address: 0xD6 Name Reset Access Description SLVM 0x7F SMBus Slave Address Mask. Defines which bits of register SMB0ADR are compared with an incoming address byte, and which bits are ignored.
Page 253: Smb0Fcn0: Smbus 0 Fifo Control
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18.4.7 SMB0FCN0: SMBus 0 FIFO Control 0 Name TFRQE TFLSH TXTH RFRQE RFLSH RXTH Access Reset SFR Page = 0x20; SFR Address: 0xC3 Name Reset Access Description TFRQE Write Request Interrupt Enable. When set to 1, an SMBus 0 interrupt will be generated any time TFRQ is logic 1.
Page 254: Smb0Fcn1: Smbus 0 Fifo Control
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18.4.8 SMB0FCN1: SMBus 0 FIFO Control 1 Name TFRQ TXNF Reserved RFRQ Reserved Access Reset SFR Page = 0x20; SFR Address: 0xC4 Name Reset Access Description TFRQ Transmit FIFO Request. Set to 1 by hardware when the number of bytes in the TX FIFO is less than or equal to the TX FIFO threshold (TXTH). Value Name Description...
Page 255: Smb0Rxln: Smbus 0 Receive Length Counter
EFM8UB3 Reference Manual System Management Bus / I2C (SMB0) 18.4.9 SMB0RXLN: SMBus 0 Receive Length Counter Name RXLN Access Reset 0x00 SFR Page = 0x20; SFR Address: 0xC5 Name Reset Access Description RXLN 0x00 SMBus Receive Length Counter. Master Receiver: This field allows firmware to set the number of bytes to receive as a master receiver (with EHACK set to 1), before stalling the bus.
Page 256: Timers (Timer0, Timer1, Timer2, Timer3, Timer4, And Timer5)
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19. Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.1 Introduction Six counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and four are 16-bit auto-reload timers for timing peripherals or for general purpose use.
Page 257: Functional Description
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.3 Functional Description 19.3.1 System Connections All five timers are capable of clocking other peripherals and triggering events in the system. The individual peripherals select which timer to use for their respective functions. Note that the Timer 2, 3, 4 and 5 high overflows apply to the full timer when operating in 16- bit mode or the high-byte timer when operating in 8-bit split mode.
Page 258: Timer 0 And Timer 1
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.3.2 Timer 0 and Timer 1 Timer 0 and Timer 1 are each implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1).
Page 259 EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.3.2.1 Operational Modes Mode 0: 13-bit Counter/Timer Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same manner as described for Timer 0.
Page 260 EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) Pre-scaled Clock SYSCLK TCLK (5 bits) (8 bits) (Interrupt Flag) GATE0 IN0PL INT0 Figure 19.1. T0 Mode 0 Block Diagram Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
Page 261 EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value.
Page 262: Timer 2, Timer 3, Timer 4, And Timer 5
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, CT0, GATE0, and TF0.
Page 263 EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) Clock Selection Clocking for each timer is configured using the TnXCLK bit field and the TnML and TnMH bits. Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external clock source divided by 8 (synchronized with SYSCLK). The maximum frequency for the external clock is: >...
Page 264 EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) Capture Source Selection Capture mode allows an external input, the low-frequency oscillator clock, comparator 0, or USB start-of-frame (SOF) events to be measured against the selected clock source. Each timer may individually select one of eight capture sources in capture mode: an external input (T2, routed through the crossbar), the low-frequency oscillator clock, comparator 0, USB start-of-frame (SOF) events, or CLUn outputs.
Page 265 EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.3.3.1 16-bit Timer with Auto-Reload When TnSPLIT is zero, the timer operates as a 16-bit timer with auto-reload. In this mode, the selected clock source increments the timer on every clock. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the timer reload registers (TMRnRLH and TMRnRLL) is loaded into the main timer count register, and the High Byte Overflow Flag (TFnH) is set.
Page 266 EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.3.3.2 8-bit Timers with Auto-Reload (Split Mode) When TnSPLIT is set, the timer operates as two 8-bit timers (TMRnH and TMRnL). Both 8-bit timers operate in auto-reload mode. TMRnRLL holds the reload value for TMRnL; TMRnRLH holds the reload value for TMRnH. The TRn bit in TMRnCN handles the run control for TMRnH.
Page 267 EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.3.3.3 Capture Mode Capture mode allows a system event to be measured against the selected clock source. When used in capture mode, the timer clocks normally from the selected clock source through the entire range of 16-bit values from 0x0000 to 0xFFFF. Setting TFnCEN to 1 enables capture mode.
Page 268: Timer 0, 1, 2, 3, 4, And 5 Control Registers
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4 Timer 0, 1, 2, 3, 4, and 5 Control Registers 19.4.1 CKCON0: Clock Control 0 Name T3MH T3ML T2MH T2ML Access Reset SFR Page = ALL; SFR Address: 0x8E Name Reset Access...
Page 269 EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) Name Reset Access Description Timer 0 Clock Select. Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1. Value Name Description PRESCALE Counter/Timer 0 uses the clock defined by the prescale field, SCA. SYSCLK Counter/Timer 0 uses the system clock.
Page 270: Ckcon1: Clock Control
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.2 CKCON1: Clock Control 1 Name Reserved T5MH T5ML T4MH T4ML Access Reset SFR Page = 0x10; SFR Address: 0xA6 Name Reset Access Description Reserved Must write reset value. T5MH Timer 5 High Byte Clock Select.
Page 271: Tcon: Timer 0/1 Control
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.3 TCON: Timer 0/1 Control Name Access Reset SFR Page = ALL; SFR Address: 0x88 (bit-addressable) Name Reset Access Description Timer 1 Overflow Flag. Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by firmware but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
Page 272: Tmod: Timer 0/1 Mode
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.4 TMOD: Timer 0/1 Mode Name GATE1 GATE0 Access Reset SFR Page = ALL; SFR Address: 0x89 Name Reset Access Description GATE1 Timer 1 Gate Control. Value Name Description DISABLED Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
Page 273: Tl0: Timer 0 Low Byte
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) Name Reset Access Description Timer 0 Mode Select. These bits select the Timer 0 operation mode. Value Name Description MODE0 Mode 0, 13-bit Counter/Timer MODE1 Mode 1, 16-bit Counter/Timer MODE2 Mode 2, 8-bit Counter/Timer with Auto-Reload MODE3...
Page 274: Th0: Timer 0 High Byte
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.7 TH0: Timer 0 High Byte Name Access Reset 0x00 SFR Page = ALL; SFR Address: 0x8C Name Reset Access Description 0x00 Timer 0 High Byte. The TH0 register is the high byte of the 16-bit Timer 0. 19.4.8 TH1: Timer 1 High Byte Name Access...
Page 275: Tmr2Cn0: Timer 2 Control
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.9 TMR2CN0: Timer 2 Control 0 Name TF2H TF2L TF2LEN TF2CEN T2SPLIT T2XCLK Access Reset SFR Page = 0x0, 0x10; SFR Address: 0xC8 (bit-addressable) Name Reset Access Description TF2H Timer 2 High Byte Overflow Flag.
Page 276: Tmr2Rll: Timer 2 Reload Low Byte
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.10 TMR2RLL: Timer 2 Reload Low Byte Name TMR2RLL Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0xCA Name Reset Access Description TMR2RLL 0x00 Timer 2 Reload Low Byte. When operating in one of the auto-reload modes, TMR2RLL holds the reload value for the low byte of Timer 2 (TMR2L).
Page 277: Tmr2H: Timer 2 High Byte
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.13 TMR2H: Timer 2 High Byte Name TMR2H Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0xCD Name Reset Access Description TMR2H 0x00 Timer 2 High Byte. In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2.
Page 278: Tmr2Cn1: Timer 2 Control 1
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.14 TMR2CN1: Timer 2 Control 1 Name RLFSEL Reserved T2CSEL Access Reset SFR Page = 0x10; SFR Address: 0xFD Name Reset Access Description RLFSEL Force Reload Select. Selects the signal that can force the Timer to reload the timer from the Timer Reload SFRs regardless of whether an over- flow has occured.
Page 279: Tmr3Cn0: Timer 3 Control 0
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.15 TMR3CN0: Timer 3 Control 0 Name TF3H TF3L TF3LEN TF3CEN T3SPLIT T3XCLK Access Reset SFR Page = 0x0, 0x10; SFR Address: 0x91 Name Reset Access Description TF3H Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00.
Page 280: Tmr3Rll: Timer 3 Reload Low Byte
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.16 TMR3RLL: Timer 3 Reload Low Byte Name TMR3RLL Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0x92 Name Reset Access Description TMR3RLL 0x00 Timer 3 Reload Low Byte. When operating in one of the auto-reload modes, TMR3RLL holds the reload value for the low byte of Timer 3 (TMR3L).
Page 281: Tmr3H: Timer 3 High Byte
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.19 TMR3H: Timer 3 High Byte Name TMR3H Access Reset 0x00 SFR Page = 0x0, 0x10; SFR Address: 0x95 Name Reset Access Description TMR3H 0x00 Timer 3 High Byte. In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3.
Page 282: Tmr3Cn1: Timer 3 Control 1
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.20 TMR3CN1: Timer 3 Control 1 Name RLFSEL STSYNC Reserved T3CSEL Access Reset SFR Page = 0x10; SFR Address: 0xFE Name Reset Access Description RLFSEL Force Reload Select. Selects the signal that can force the Timer to reload the timer from the Timer Reload SFRs regardless of whether an over- flow has occured.
Page 283 EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) Name Reset Access Description CLU2_OUT Capture high-to-low transitions on the configurable logic unit 2 synchro- nous output. CLU3_OUT Capture high-to-low transitions on the configurable logic unit 3 synchro- nous output. silabs.com | Building a more connected world.
Page 284: Tmr4Cn0: Timer 4 Control 0
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.21 TMR4CN0: Timer 4 Control 0 Name TF4H TF4L TF4LEN TF4CEN T4SPLIT T4XCLK Access Reset SFR Page = 0x10; SFR Address: 0x98 (bit-addressable) Name Reset Access Description TF4H Timer 4 High Byte Overflow Flag. Set by hardware when the Timer 4 high byte overflows from 0xFF to 0x00.
Page 285: Tmr4Rll: Timer 4 Reload Low Byte
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.22 TMR4RLL: Timer 4 Reload Low Byte Name TMR4RLL Access Reset 0x00 SFR Page = 0x10; SFR Address: 0xA2 Name Reset Access Description TMR4RLL 0x00 Timer 4 Reload Low Byte. When operating in one of the auto-reload modes, TMR4RLL holds the reload value for the low byte of Timer 4 (TMR4L).
Page 286: Tmr4H: Timer 4 High Byte
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.25 TMR4H: Timer 4 High Byte Name TMR4H Access Reset 0x00 SFR Page = 0x10; SFR Address: 0xA5 Name Reset Access Description TMR4H 0x00 Timer 4 High Byte. In 16-bit mode, the TMR4H register contains the high byte of the 16-bit Timer 4. In 8-bit mode, TMR4H contains the 8-bit high byte timer value.
Page 287: Tmr4Cn1: Timer 4 Control 1
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.26 TMR4CN1: Timer 4 Control 1 Name RLFSEL STSYNC Reserved T4CSEL Access Reset SFR Page = 0x10; SFR Address: 0xFF Name Reset Access Description RLFSEL Force Reload Select. Selects the signal that can force the Timer to reload the timer from the Timer Reload SFRs regardless of whether an over- flow has occured.
Page 288: Tmr5Rll: Timer 5 Reload Low Byte
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) Name Reset Access Description CLU3_OUT Capture high-to-low transitions on the configurable logic unit 3 synchro- nous output. 19.4.27 TMR5RLL: Timer 5 Reload Low Byte Name TMR5RLL Access Reset 0x00 SFR Page = 0x10;...
Page 289: Tmr5H: Timer 5 High Byte
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.30 TMR5H: Timer 5 High Byte Name TMR5H Access Reset 0x00 SFR Page = 0x10; SFR Address: 0xD5 Name Reset Access Description TMR5H 0x00 Timer 5 High Byte. In 16-bit mode, the TMR5H register contains the high byte of the 16-bit Timer 5. In 8-bit mode, TMR5H contains the 8-bit high byte timer value.
Page 290: Tmr5Cn0: Timer 5 Control 0
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.31 TMR5CN0: Timer 5 Control 0 Name TF5H TF5L TF5LEN TF5CEN T5SPLIT T5XCLK Access Reset SFR Page = 0x10; SFR Address: 0xC0 (bit-addressable) Name Reset Access Description TF5H Timer 5 High Byte Overflow Flag. Set by hardware when the Timer 5 high byte overflows from 0xFF to 0x00.
Page 291: Tmr5Cn1: Timer 5 Control 1
EFM8UB3 Reference Manual Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) 19.4.32 TMR5CN1: Timer 5 Control 1 Name RLFSEL Reserved T5CSEL Access Reset SFR Page = 0x10; SFR Address: 0xF1 Name Reset Access Description RLFSEL Force Reload Select. Selects the signal that can force the Timer to reload the timer from the Timer Reload SFRs regardless of whether an over- flow has occured.
Page 292: Universal Asynchronous Receiver/Transmitter 1 (Uart1)
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20. Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.1 Introduction UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates. A received data FIFO allows UART1 to receive multiple bytes before data is lost and an overflow occurs.
Page 293: Functional Description
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.3 Functional Description 20.3.1 Baud Rate Generation The UART1 baud rate is generated by a dedicated 16-bit timer which runs from the controller’s core clock (SYSCLK), and has prescaler options of 1, 4, 12, or 48. The timer and prescaler options combined allow for a wide selection of baud rates over many SYSCLK fre- quencies.
Page 294: Flow Control
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.3.3 Flow Control The UART provides hardware flow control via the CTS and RTS pins. CTS and RTS may be individually enabled using the crossbar, may be operated independently of one another, and are active only when enabled through the crossbar. The CTS pin is an input to the device.
Page 295 EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) Using the Transmit FIFO Prior to using the transmit FIFO, the appropriate configuration settings for the application should be established: • The TXTH field should be adjusted to the desired level. TXTH determines when the hardware will generate write requests and set the TXRQ flag.
Page 296 EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) Using the Receive FIFO The receive FIFO also has configuration settings which should be established prior to enabling UART reception: • The RXTH field should be adjusted to the desired level. RXTH determines when the hardware will generate read requests and set the RXRQ flag.
Page 297: Multiprocessor Communications
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.3.6 Multiprocessor Communications UART1 supports multiprocessor communication between a master processor and one or more slave processors by special use of the extra data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its extra bit is logic 1;...
Page 298: Routing Rx Through Configurable Logic
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.3.9 Routing RX Through Configurable Logic The RX1 input of the UART is routed through the crossbar by default. It is also possible to route the RX input to the output of CLU0, CLU1 or CLU2.
Page 299: Uart1 Control Registers
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.4 UART1 Control Registers 20.4.1 SCON1: UART1 Serial Port Control Name PERR Reserved Access Reset Varies SFR Page = 0x0, 0x20; SFR Address: 0x98 (bit-addressable) Name Reset Access Description Receive FIFO Overrun Flag. This bit indicates a receive FIFO overrun condition, where an incoming character is discarded due to a full FIFO.
Page 300 EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) Name Reset Access Description Receive Interrupt Flag. Set to 1 by hardware when a byte of data has been received by UART1 (set at the STOP bit sampling time). RI remains set while the receive FIFO contains any data.
Page 301: Smod1: Uart1 Mode
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.4.2 SMOD1: UART1 Mode Name Access Reset SFR Page = 0x20; SFR Address: 0x93 Name Reset Access Description Multiprocessor Communication Enable. This function is not available when hardware parity is enabled. Value Name Description MULTI_DISABLED...
Page 302: Sbuf1: Uart1 Serial Port Data Buffer
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) Name Reset Access Description ENABLED Enable the extra bit. Stop Bit Length. Value Name Description SHORT Short: Stop bit is active for one bit time. LONG Long: Stop bit is active for two bit times (data length = 6, 7, or 8 bits) or 1.5 bit times (data length = 5 bits).
Page 303: Sbcon1: Uart1 Baud Rate Generator Control
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.4.4 SBCON1: UART1 Baud Rate Generator Control Name Reserved BREN Reserved Access Reset SFR Page = 0x20; SFR Address: 0x94 Name Reset Access Description Reserved Must write reset value. BREN Baud Rate Generator Enable. Value Name Description...
Page 304: Sbrll1: Uart1 Baud Rate Generator Low Byte
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.4.6 SBRLL1: UART1 Baud Rate Generator Low Byte Name Access Reset 0x00 SFR Page = 0x20; SFR Address: 0x95 Name Reset Access Description 0x00 UART1 Baud Rate Reload Low. This field is the low byte of the 16-bit UART1 baud rate generator. The high byte of the baud rate generator should be writ- ten first, then the low byte.
Page 305: Uart1Fcn0: Uart1 Fifo Control
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.4.7 UART1FCN0: UART1 FIFO Control 0 Name TFRQE TFLSH TXTH RFRQE RFLSH RXTH Access Reset SFR Page = 0x20; SFR Address: 0x9D Name Reset Access Description TFRQE Write Request Interrupt Enable. When set to 1, a UART1 interrupt will be generated any time TFRQ is logic 1. Value Name Description...
Page 306 EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) Name Reset Access Description RFRQ will be set if the RX FIFO contains more than one byte. RFRQ will be set if the RX FIFO contains more than two bytes. THREE RFRQ will be set if the RX FIFO contains more than three bytes. silabs.com | Building a more connected world.
Page 307: Uart1Fcn1: Uart1 Fifo Control
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.4.8 UART1FCN1: UART1 FIFO Control 1 Name TFRQ TXNF TXHOLD RFRQ RXTO Access Reset SFR Page = 0x20; SFR Address: 0xD8 (bit-addressable) Name Reset Access Description TFRQ Transmit FIFO Request. Set to 1 by hardware when the number of bytes in the TX FIFO is less than or equal to the TX FIFO threshold (TXTH). Value Name Description...
Page 308: Uart1Fct: Uart1 Fifo Count
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) Name Reset Access Description RXTO Receive Timeout. This field defines the length of the timeout on the RX FIFO. If the RX FIFO is not empty but the number of bytes in the FIFO is not enough to generate a Receive FIFO request, an RFRQ interrupt will be generated after the specified number of idle frames.
Page 309: Uart1Lin: Uart1 Lin Configuration
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) 20.4.10 UART1LIN: UART1 LIN Configuration Name AUTOBDE BREAKDN SYNCTO SYNCD LINMDE BREAKDNIE SYNCTOIE SYNCDIE Access Reset SFR Page = 0x20; SFR Address: 0x9E Name Reset Access Description AUTOBDE Auto Baud Detection Enable. This bit enables auto-baud detection.
Page 310: Uart1Pcf: Uart1 Configuration
EFM8UB3 Reference Manual Universal Asynchronous Receiver/Transmitter 1 (UART1) Name Reset Access Description ENABLED A valid LIN break field and delimiter must be detected prior to the hard- ware state machine recognizing a sync word and performing autobaud. BREAKDNIE LIN Break Done Interrupt Enable. Enables the break done interrupt source.
Page 311: Universal Serial Bus (Usb0)
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21. Universal Serial Bus (USB0) 21.1 Introduction The USB0 peripheral provides a full-speed USB 2.0 compliant device controller and PHY with additional Low Energy USB features. The device supports both full-speed (12MBit/s) and low speed (1.5MBit/s) operation, and includes a dedicated USB oscillator with clock re- covery mechanism for crystal-free operation.
Page 312: Functional Description
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.3 Functional Description 21.3.1 Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes. Table 21.1.
Page 313: Register Access
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.3.5 Register Access Many of the USB0 controller registers are accessed indirectly through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. Endpoint control/ status registers are accessed by first writing the USB register INDEX with the target endpoint number.
Page 314 EFM8UB3 Reference Manual Universal Serial Bus (USB0) USB Register Name USB Register Address Description FRAMEH 0x0D Frame Number High Byte INDEX 0x0E Endpoint Index Selection CLKREC 0x0F Clock Recovery Control EENABLE 0x1E Endpoint Enable FIFOn 0x20-0x23 Endpoints0-3 FIFOs Indexed Registers E0CSR 0x11 Endpoint0 Control / Status...
Page 315: Fifo Management
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.3.6 FIFO Management 1024 bytes of on-chip XRAM are used as FIFO space for the USB block. This FIFO space is split between Endpoints0-3. Endpoint0 is 64 bytes long, Endpoint1 is 128 bytes long, Endpoint2 is 256 bytes long, and Endpoint3 is 512 bytes long. FIFO space allocated for Endpoints1-3 is also configurable as IN, OUT, or both (split mode: half IN, half OUT).
Page 316: Function Addressing
EFM8UB3 Reference Manual Universal Serial Bus (USB0) FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for Split Mode, dou- ble buffering may be enabled for the IN Endpoint and/or the OUT endpoint.
Page 317: Function Configuration And Control
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.3.8 Function Configuration and Control The USB register POWER is used to configure and control the USB block at the device level (enable/disable, Reset/Suspend/Resume handling, etc.). USB Reset: The USBRST bit is set to 1 by hardware when Reset signaling is detected on the bus. Upon this detection, the following occur: 1.
Page 318: Endpoint
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.3.11 Endpoint 0 Endpoint0 is managed through the USB register E0CSR. The INDEX register must be loaded with 0x00 to access the E0CSR register. An Endpoint0 interrupt is generated when one of the following occurs: •...
Page 319: Endpoints 1, 2, And 3
EFM8UB3 Reference Manual Universal Serial Bus (USB0) Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit to 1 and generate an Endpoint0 interrupt. Following this interrupt, firmware should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit to 1.
Page 320 EFM8UB3 Reference Manual Universal Serial Bus (USB0) Operating Endpoints 1-3 as IN Isochronous Endpoints When the ISO bit is set to 1, the target endpoint operates in Isochronous (ISO) mode. Once an endpoint has been configured for ISO IN mode, the host will send one IN token (data request) per frame; the location of data within each frame may vary. Because of this, it is recommended that double buffering be enabled for ISO IN endpoints.
Page 321: Low Energy Mode
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.3.13 Low Energy Mode The USB module has controls for automatically optimizing the power used by the block according to the current bus activity. The affec- ted portions of the hardware and when the hardware uses the low energy mode are both configured using fields in the USB0AEC regis- ter.
Page 322 EFM8UB3 Reference Manual Universal Serial Bus (USB0) Detection of SDP, DCP, and CDP The most common and straightforward usage of the charger detection block is to determine the type of USB port to which the device has been connected. Each type of port has different load profile, maximum current, and communications capabilities, per the specifica- tion.
Page 323 EFM8UB3 Reference Manual Universal Serial Bus (USB0) Enable VBUS, Enable DCD and PD VBUS Detected Firmware Action Hardware Action Data Contact Detection Optional Interrupt Contact Detected or Timeout Primary Detection PD Complete Not SDP Enable SD? Must Assume Secondary Detection DCP Profile SD Complete SDP Detected...
Page 324 EFM8UB3 Reference Manual Universal Serial Bus (USB0) Atypical Charger Detection It is possible to detect ACA chargers, as well as certain chargers that do not comply with the USB specification, using additional resour- ces on the device. Accessory charging adapters (ACA) chargers use a resistor to ground on a special ID pin and a specific voltage on the USB D- pin to encode the type of ACA and its capabilities.
Page 325 EFM8UB3 Reference Manual Universal Serial Bus (USB0) Enable VBUS Detection VBUS Detected Check For Non- Compliant Charger Non-compliant charger detected Enable DCD and PD Handle Non- Compliant Charger Data Contact Detection Firmware Action Contact Detected or Timeout Hardware Action Primary Detection Optional Interrupt Optional Firmware PD Complete...
Page 326: Usb0 Control Registers
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4 USB0 Control Registers 21.4.1 USB0XCN: USB0 Transceiver Control Name PREN PHYEN SPEED PHYTST DFREC Access Reset SFR Page = 0x20; SFR Address: 0xB3 Name Reset Access Description PREN Internal Pull-up Resistor Enable. The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit.
Page 327: Usb0Adr: Usb0 Indirect Address
EFM8UB3 Reference Manual Universal Serial Bus (USB0) Name Reset Access Description DIFFERENTIAL_ONE Differential 1 signalling on the bus. D+ Signal Status. This bit indicates the current logic level of the D+ pin. Value Name Description D+ signal currently at logic 0. HIGH D+ signal currently at logic 1.
Page 328: Usb0Dat: Usb0 Data
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.3 USB0DAT: USB0 Data Name USB0DAT Access Reset 0x00 SFR Page = ALL; SFR Address: 0xAF Name Reset Access Description USB0DAT 0x00 USB0 Data. This register is used to indirectly read and write the USB0 register targeted by USB0ADDR. 21.4.4 INDEX: USB0 Endpoint Index Name Reserved...
Page 329: Clkrec: Usb0 Clock Recovery Control
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.5 CLKREC: USB0 Clock Recovery Control Name CRSSEN CRLOW Reserved Access Reset 0x0F Indirect Address: 0x0F Name Reset Access Description Clock Recovery Enable. This bit enables/disables the USB clock recovery feature. Value Name Description DISABLED Disable clock recovery.
Page 330: Fifo0: Usb0 Endpoint 0 Fifo Access
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.6 FIFO0: USB0 Endpoint 0 FIFO Access Name FIFODATA Access Reset 0x00 Indirect Address: 0x20 Name Reset Access Description FIFODATA 0x00 Endpoint 0 FIFO Access. Writing to this FIFO address loads data into the IN FIFO for Endpoint 0. Reading from the FIFO address reads data from the Endpoint 0 OUT FIFO.
Page 331: Fifo3: Usb0 Endpoint 3 Fifo Access
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.9 FIFO3: USB0 Endpoint 3 FIFO Access Name FIFODATA Access Reset 0x00 Indirect Address: 0x23 Name Reset Access Description FIFODATA 0x00 Endpoint 3 FIFO Access. Writing to this FIFO address loads data into the IN FIFO for Endpoint 3. Reading from the FIFO address reads data from the Endpoint 3 OUT FIFO.
Page 332: Power: Usb0 Power
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.11 POWER: USB0 Power Name ISOUD Reserved USBINH USBRST RESUME SUSMD SUSEN Access Reset Indirect Address: 0x01 Name Reset Access Description ISOUD Isochronous Update Mode. This bit affects all IN Isochronous endpoints. Value Name Description IN_TOKEN...
Page 333: Framel: Usb0 Frame Number Low
EFM8UB3 Reference Manual Universal Serial Bus (USB0) Name Reset Access Description SUSPENDED USB0 in suspend mode. SUSEN Suspend Detection Enable. Value Name Description DISABLED Disable suspend detection. USB0 will ignore suspend signaling on the bus. ENABLED Enable suspend detection. USB0 will enter suspend mode if it detects suspend signaling on the bus.
Page 334: In1Int: Usb0 In Endpoint Interrupt
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.14 IN1INT: USB0 IN Endpoint Interrupt Name Reserved Access Reset Indirect Address: 0x02 Name Reset Access Description Reserved Must write reset value. IN Endpoint 3 Interrupt Flag. This bit is cleared when firmware reads the IN1INT register. Value Name Description...
Page 335: Out1Int: Usb0 Out Endpoint Interrupt
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.15 OUT1INT: USB0 OUT Endpoint Interrupt Name Reserved OUT3 OUT2 OUT1 Reserved Access Reset Indirect Address: 0x04 Name Reset Access Description Reserved Must write reset value. OUT3 OUT Endpoint 3 Interrupt Flag. This bit is cleared when firmware reads the OUT1INT register. Value Name Description...
Page 336: Cmint: Usb0 Common Interrupt
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.16 CMINT: USB0 Common Interrupt Name Reserved RSTINT RSUINT SUSINT Access Reset Indirect Address: 0x06 Name Reset Access Description Reserved Must write reset value. Start of Frame Interrupt Flag. This bit is set by hardware when a SOF token is received. This interrupt event is synthesized by hardware: an interrupt will be generated when hardware expects to receive a SOF event, even if the actual SOF signal is missed or corrupted.
Page 337: In1Ie: Usb0 In Endpoint Interrupt Enable
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.17 IN1IE: USB0 IN Endpoint Interrupt Enable Name Reserved IN3E IN2E IN1E EP0E Access Reset Indirect Address: 0x07 Name Reset Access Description Reserved Must write reset value. IN3E IN Endpoint 3 Interrupt Enable. Value Name Description...
Page 338: Out1Ie: Usb0 Out Endpoint Interrupt Enable
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.18 OUT1IE: USB0 OUT Endpoint Interrupt Enable Name Reserved OUT3E OUT2E OUT1E Reserved Access Reset Indirect Address: 0x09 Name Reset Access Description Reserved Must write reset value. OUT3E OUT Endpoint 3 Interrupt Enable. Value Name Description...
Page 339: Cmie: Usb0 Common Interrupt Enable
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.19 CMIE: USB0 Common Interrupt Enable Name Reserved SOFE RSTINTE RSUINTE SUSINTE Access Reset Indirect Address: 0x0B Name Reset Access Description Reserved Must write reset value. SOFE Start of Frame Interrupt Enable. Value Name Description DISABLED...
Page 340: E0Csr: Usb0 Endpoint0 Control
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.20 E0CSR: USB0 Endpoint0 Control Name SSUEND SOPRDY SDSTL SUEND DATAEND STSTL INPRDY OPRDY Access Reset Indirect Address: 0x11 Name Reset Access Description SSUEND Serviced Setup End. Firmware should set this bit to 1 after servicing a setup end (SUEND) event. Hardware clears the SUEND bit when firm- ware writes 1 to SSUEND.
Page 341: E0Cnt: Usb0 Endpoint0 Data Count
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.21 E0CNT: USB0 Endpoint0 Data Count Name Reserved E0CNT Access Reset 0x00 Indirect Address: 0x16 Name Reset Access Description Reserved Must write reset value. E0CNT 0x00 Endpoint 0 Data Count. This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This number is only valid while OPRDY is 1.
Page 342: Eenable: Usb0 Endpoint Enable
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.22 EENABLE: USB0 Endpoint Enable Name Reserved EEN3 EEN2 EEN1 Reserved Access Reset Indirect Address: 0x1E Name Reset Access Description Reserved Must write reset value. EEN3 Endpoint 3 Enable. This bit enables or disables Endpoint 3. Value Name Description...
Page 343: Eincsrl: Usb0 In Endpoint Control Low
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.23 EINCSRL: USB0 IN Endpoint Control Low Name Reserved CLRDT STSTL SDSTL FLUSH UNDRUN FIFONE INPRDY Access Reset Indirect Address: 0x11 Name Reset Access Description Reserved Must write reset value. CLRDT Clear Data Toggle. STSTL Sent Stall Flag.
Page 344: Eincsrh: Usb0 In Endpoint Control High
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.24 EINCSRH: USB0 IN Endpoint Control High Name DBIEN DIRSEL Reserved FCDT SPLIT Reserved Access Reset Indirect Address: 0x12 Name Reset Access Description DBIEN IN Endpoint Double-Buffer Enable. Value Name Description DISABLED Disable double-buffering for the selected IN endpoint. ENABLED Enable double-buffering for the selected IN endpoint.
Page 345: Eoutcsrl: Usb0 Out Endpoint Control Low
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.25 EOUTCSRL: USB0 OUT Endpoint Control Low Name CLRDT STSTL SDSTL FLUSH DATERR OVRUN FIFOFUL OPRDY Access Reset Indirect Address: 0x14 Name Reset Access Description CLRDT Clear Data Toggle. Firmware should write 1 to this bit to reset the IN Endpoint data toggle to 0. It always reads 0. STSTL Sent Stall Flag.
Page 346: Eoutcsrh: Usb0 Out Endpoint Control High
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.26 EOUTCSRH: USB0 OUT Endpoint Control High Name DBOEN Reserved Access Reset 0x00 Indirect Address: 0x15 Name Reset Access Description DBOEN Double-Buffer Enable. Value Name Description DISABLED Disable double-buffering for the selected OUT endpoint. ENABLED Enable double-buffering for the selected OUT endpoint.
Page 347: Eoutcnth: Usb0 Out Endpoint Count High
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.28 EOUTCNTH: USB0 OUT Endpoint Count High Name Reserved EOCH Access Reset 0x00 Indirect Address: 0x17 Name Reset Access Description Reserved Must write reset value. EOCH OUT Endpoint Count High. EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO.
Page 348: Usb0Cf: Usb0 Configuration
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.29 USB0CF: USB0 Configuration Name VBUSEN VBUSIE VBUSI Reserved USBCLK Access Reset SFR Page = 0x20; SFR Address: 0xB5 Name Reset Access Description VBUSEN VBUS Sense Enable. Enables the VBUS function on the VBUS I/O line. Value Name Description...
Page 349 EFM8UB3 Reference Manual Universal Serial Bus (USB0) Name Reset Access Description NOCLOCK USB0 clock (USB0CLK) is turned off. silabs.com | Building a more connected world. Rev. 0.2 | 349...
Page 350: Usb0Aec: Usb0 Advanced Energy Control
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.30 USB0AEC: USB0 Advanced Energy Control Name LEMSTA XCVRMD OSCMD Reserved LEMCN Access Reset SFR Page = 0x20; SFR Address: 0xB2 Name Reset Access Description LEMSTA Low Energy Mode Status. This bit indicates whether low energy mode mode is active, due to current USB bus conditions. Value Name Description...
Page 351: Usb0Cdcf: Usb0 Charger Detect Configuration
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.31 USB0CDCF: USB0 Charger Detect Configuration Name Reserved SDIE PDIE DCDIE Reserved Access Reset SFR Page = 0x20; SFR Address: 0xB6 Name Reset Access Description Reserved Must write reset value. SDIE SD Interrupt Enable. Enables the SDI flag as an interrupt source.
Page 352: Usb0Cdcn: Usb0 Charger Detect Control
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.32 USB0CDCN: USB0 Charger Detect Control Name Reserved CHDEN SDEN PDEN DCDEN Access Reset SFR Page = 0x20; SFR Address: 0xBE Name Reset Access Description Reserved Must write reset value. CHDEN Charger Detection Enable. This bit enables the charger detect circuitry.
Page 353: Usb0Cdsta: Usb0 Charger Detect Status
EFM8UB3 Reference Manual Universal Serial Bus (USB0) 21.4.33 USB0CDSTA: USB0 Charger Detect Status Name DCDI DCDTO Access Reset SFR Page = 0x20; SFR Address: 0xBF Name Reset Access Description USB Charger Detection Error. This bit indicates that an error occurred during the charger detect sequence. This bit will be set if the VBUS signal is dis- connected while the charger detect circuit is active.
Page 354 EFM8UB3 Reference Manual Universal Serial Bus (USB0) Name Reset Access Description DCD operation has completed. If DCDIE is set to 1 a charger detect in- terrupt may be generated. This flag must be cleared by firmware. DCDTO Data Contact Detection Timeout. This bit is set at the completion of a DCD operation if the operation was stopped due to DCD timeout.
Page 355: Watchdog Timer (Wdt0)
EFM8UB3 Reference Manual Watchdog Timer (WDT0) 22. Watchdog Timer (WDT0) 22.1 Introduction The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator. A WDT overflow forces the MCU into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset.
Page 356 EFM8UB3 Reference Manual Watchdog Timer (WDT0) Disabling the WDT Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment illustrates disabling the WDT: CLR EA ; disable all interrupts MOV WDTCN,#0DEh ; disable software watchdog timer MOV WDTCN,#0ADh ;...
Page 357: Wdt0 Control Registers
EFM8UB3 Reference Manual Watchdog Timer (WDT0) Synchronization The watchdog timer is controlled via the WDTCN control register using commands. Commands require synchronization between the system clock and WDT clock source, the divided LFOSC0 clock. The table below lists each WDT command and the number of clock periods from the specified clock source for the command to take effect.
Page 358: C2 Debug And Programming Interface
EFM8UB3 Reference Manual C2 Debug and Programming Interface 23. C2 Debug and Programming Interface 23.1 Introduction The device includes an on-chip Silicon Labs 2-Wire (C2) debug interface that allows flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the device and a host system.
Page 359: C2 Interface Registers
EFM8UB3 Reference Manual C2 Debug and Programming Interface 23.4 C2 Interface Registers 23.4.1 C2ADD: C2 Address Name C2ADD Access Reset 0x00 This register is part of the C2 protocol. Name Reset Access Description C2ADD 0x00 C2 Address. The C2ADD register is accessed via the C2 interface. The value written to C2ADD selects the target data register for C2 Data Read and Data Write commands.
Page 360: C2Fpctl: C2 Flash Programming Control
EFM8UB3 Reference Manual C2 Debug and Programming Interface 23.4.4 C2FPCTL: C2 Flash Programming Control Name C2FPCTL Access Reset 0x00 C2 Address: 0x02 Name Reset Access Description C2FPCTL 0x00 Flash Programming Control Register. This register is used to enable flash programming via the C2 interface. To enable C2 flash programming, the following co- des must be written in order: 0x02, 0x01.
Page 361: Revision History
EFM8UB3 Reference Manual Revision History 24. Revision History Revision 0.2 October, 2018 • Updated the WDT block diagram in 22.1 Introduction. • Updated the WDT behaviour for all the commands in 22.3 Using the Watchdog Timer section. • Added Synchronization section in 22.3 Using the Watchdog Timer.
Page 362 Trademark Information Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, ISOmodem®, Micrium, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®, Zentri, Z-Wave, and others are trademarks or...

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Efm8ub3

Silicon Laboratories EFM8 Series Reference Manual

1 System Overview

2 Memory

3 Special Function Registers

4 Flash Memory

5 Device Identification

6 Interrupts

7 Power Management and Internal Regulators

8 Clocking and Oscillators

9 Reset Sources and Power Supply Monitor

10 Microcontroller Core

11 Port I/O, Crossbar, External Interrupts, and Port Match

12 Analog-To-Digital Converter (ADC0)

13 Comparators (CMP0 and CMP1)

14 Configurable Logic Units (CLU0, CLU1, CLU2, CLU3)

15 Cyclic Redundancy Check (CRC0)

16 Programmable Counter Array (PCA0)

17 Serial Peripheral Interface (SPI0)

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