Silicon Laboratories I2C Manual page 10

Si5338
Table 6. Input and Output Clock Characteristics (Continued)
(V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
DD
Parameter
CMOS Output
Resistance
SSTL Output
Resistance
HSTL Output
Resistance
CMOS Output
8
Voltage
SSTL Output Voltage
HSTL Output Voltage
5
Duty Cycle
Notes:
1. Use an external 100  resistor to provide load termination for a differential clock. See Figure 3.
2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.
3. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
5. Not in PLL bypass mode.
6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis
Stages" on page 18.
7. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver.
8. Includes effect of internal series 22  resistor.
10
A
Symbol Test Condition
V 4 mA load
OH
V 4 mA load
OL
V SSTL-3
OH
VDDOx = 2.97 to
V
OL
3.63 V
V SSTL-2
OH
VDDOx = 2.25 to
V
OL
2.75 V
V SSTL-18
OH
VDDOx = 1.71 to
V
OL
1.98 V
V VDDO = 1.4 to
OH
1.6 V
V
OL
DC
= –40 to 85 °C)
Min
—
—
—
VDDO – 0.3
0.45xVDDO+0.41
—
0.5xVDDO+0.41
—
0.5xVDDO+0.34
—
0.5xVDDO+0.3
—
45
Rev. 1.2
Typ Max Units
50 —
50 —
50 —
—
— 0.3
— —
— 0.45xVDDO
–0.41
— —
— 0.5xVDDO–
0.41
—
— 0.5xVDDO–
0.34
— —
— 0.5xVDDO –
0.3
— 55



V
V
V
V
V
V
V
V
V
V
%