Silicon Laboratories SI5324 Specification Sheet

Video Timing Solutions
D E S C R I P T I O N
Silicon Laboratories' Si5324 Any-Rate Precision Clock is the industry's lowest jitter, most
highly integrated video clock IC optimized for genlock applications. Based on Silicon Labs'
patented DSPLL® technology, the Si5324 has a fully integrated, digitally programmable
loop filter that supports loop bandwidths ranging from 4 Hz to 525 Hz as well as a low
phase noise internal VCO. By consuming less than 10% of the overall 3G-SDI jitter budget
required in next generation video applications, the Si5324 simplifies design and eases
system-level SDI jitter testing. In addition, the Si5324 provides any-rate frequency
flexibility by generating virtually any output frequency from 2 kHz to 1.4 GHz from any
input frequency ranging from 2 kHz to 710 MHz enabling a single IC design for multi-rate
video applications.
Application Example: Production Video Switcher
Si554
VCXO
Cable
Equalizer
SDI
3G/SD/
HD-SDI
Reclocker Deserializer
Si554
VCXO
SDI
3G/SD/
HD-SDI
Reclocker Deserializer
Cable
Equalizer
Sync
Separator
Sync Input
Master Sync Generator
F R E Q U E N C Y F L E X I B L E G E N L O C K S O L U T I O N
Video
Processor/
Buffer
YCbCr
SDI
Pclk, hvf
YCbCr
SDI
Pclk, hvf
Si5338
Si5324
HSYNC
Clock
Any-Rate
Generator
Clock
Genlock
F U L L Y I N T E G R A T E D ,
Si590
XO
Cable Driver
YCbCr
SDI
Serializer
3G/SD/
HD-SDI
Sample Clock
3G-SDI Reference Clock
HD (74.25 MHz)
HD (74.1758 MHz)
Audio (24.576 MHz)
Processor (66.66 MHz)
F E A T U R E S
• Generates any frequency from 2 kHz to
945 MHz and select frequencies to 1.4 GHz
from an input frequency of 2 kHz to 710 MHz
• Ultra-low jitter 0.58 ps RMS, 5 ps pk-pk at
3G-SDI (10 Hz to 20 MHz)
• Digitally programmable loop bandwidth with
fastlock (4 Hz to 525 Hz)
• Meets 3G-SDI (SMPTE 424M) for timing and
alignment jitter limits
• Genlock, free-run, and digital hold
• Hitless switching between input clocks with
phase build-out
• Manual or automatic (revertive, non-
revertive) input clock selection
• LOL, LOS and FOS alarm outputs
• Configurable signal format per output
(LVPECL, LVDS, CML, CMOS)
• I²C/SPI programmable
• Single supply 1.8, 2.5 or 3.3 V ±10%
with high PSNR
• Pb-free, RoHS compliant
A P P L I C A T I O N S
• Video or audio genlock and synchronization
• FPGA SDI SerDes recovered clock generation
• Triple rate 3G/HD/SD-SDI SerDes
• Video capture, conversion, editing and
distribution
• Digital audio or video recording and
playback devices
• Video server
• Video format converter
• Video switcher and frame synchronizer
S O L U T I O N S G U I D E
ANY-RATE
FREQUENCY SYNTHESIS
IN A SINGLE IC