Silicon Laboratories I2C Manual page 14

Si5338
Table 12. Jitter Specifications
(V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
DD
Parameter
Deterministic Jitter
Total Jitter
(12 kHz–20 MHz)
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
4. D for PCI and GbE is < 5 ps pp
J
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is measured with the Intel Clock Jitter Tool, Ver. 1.6.4.
7. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5 MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 2
Table 13. itter Specifications, Clock Buffer Mode (PLL Bypass)*
(V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
DD
Parameter
Additive Phase Jitter
(12 kHz–20 MHz)
Additive Phase Jitter
(50 kHz–80 MHz)
*Note: All outputs are in Clock Buffer mode (PLL Bypass).
14
1,2,3
(Continued)
= –40 to 85 °C)
A
Symbol Test Condition
Output MultiSynth
operated in fractional
7
mode
D
J
Output MultiSynth
operated in integer
7
mode
Output MultiSynth
operated in fractional
7
mode
T = D +14xR
J J J
9
(See Note )
Output MultiSynth
operated in integer
7
mode
= –40 to 85 °C)
A
Symbol Test Condition
0.7 V pk-pk differential input
clock at 622.08 MHz with
t
RPHASE
70 ps rise/fall time
0.7 V pk-pk differential input
clock at 622.08 MHz with
t
RPHASEWB
70 ps rise/fall time
Rev. 1.2
Min
—
—
—
—
12
rising edges.
Min
—
—
Typ Max Unit
3 15 ps pk-pk
2 10 ps pk-pk
13 36 ps pk-pk
12 20 ps pk-pk
Typ Max Unit
0.165 — ps RMS
0.225 — ps RMS