Si5338
8. Device Pinout by Part Number
The Si5338 is orderable in three different speed grades: Si5338A/D/G/K/N have a maximum output clock
frequency limit of 710 MHz. Si5338B/E/H/L/P have a maximum output clock frequency of 350 MHz. Si5338C/F/J/
M/Q have a maximum output clock frequency of 200 MHz.
Devices are also orderable according to the pin control functions available on Pins 3 and 4:
CLKIN—single-ended clock input
I2C_LSB—determines the LSB bit of the 7-bit I
FINC—frequency increment pin
FDEC—frequency decrement pin
PINC—phase increment pin
PDEC—phase decrement pin
FDBK—single-ended feedback input
OEB—output enable
Pin # Si5338A: 710 MHz
Si5338B: 350 MHz
Si5338C: 200 MHz
1
1
CLKIN
1
2
CLKINB
2
3
CLKIN
4
I2C_LSB
4
5
FDBK
4
6
FDBKB
7
VDD
8
INTR
9
CLK3B
10
CLK3A
11
VDDO3
12
SCL
13
CLK2B
14
CLK2A
15
VDDO2
16
VDDO1
Notes:
1. CLKIN/CLKINB on pins 1 and 2 are differential clock inputs or XTAL inputs.
2. CLKIN on pin 3 is a single-ended clock input.
3. FDBK on pin 4 is a single-ended feedback input.
4. FDBK/FDBKB on pins 5 and 6 are differential feedback inputs.
36
2
C address
Table 17. Pin Function by Part Number
Si5338D: 710 MHz
Si5338G: 710 MHz
Si5338E: 350 MHz
Si5338H: 350 MHz
Si5338F: 200 MHz
Si5338J: 200 MHz
1
CLKIN
1
CLKINB
PINC
PDEC
4
FDBK
4
FDBKB
VDD
INTR
CLK3B
CLK3A
VDDO3
SCL
CLK2B
CLK2A
VDDO2
VDDO1
Rev. 1.2
Si5338K: 710 MHz
Si5338L: 350 MHz
Si5338M: 200 MHz
1
CLKIN
CLKIN
1
CLKINB
CLKINB
FINC
OEB
FDEC
I2C_LSB
4
FDBK
FDBK
4
FDBKB
FDBKB
VDD
VDD
INTR
INTR
CLK3B
CLK3B
CLK3A
CLK3A
VDDO3
VDDO3
SCL
SCL
CLK2B
CLK2B
CLK2A
CLK2A
VDDO2
VDDO2
VDDO1
VDDO1
Si5338N: 710 MHz
Si5338P: 350 MHz
Si5338Q: 200 MHz
1
1
CLKIN
1
1
CLKINB
2
CLKIN
3
FDBK
4
4
FDBK
4
4
FDBKB
VDD
INTR
CLK3B
CLK3A
VDDO3
SCL
CLK2B
CLK2A
VDDO2
VDDO1
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