Silicon Laboratories I2C Manual

Silicon Laboratories I2C Manual

Programmable any-frequency, any-output quad clock generator

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2
I
C - P
R O GRA MM A B LE
Q
C
UAD
LOCK
Features
Low power MultiSynth™ technology
enables independent, any-frequency
synthesis on four differential output
drivers
Highly-configurable output drivers with
up to four differential outputs, eight
single-ended clock outputs, or a
combination of both
Low phase jitter of 0.7 ps RMS typ
High precision synthesis allows true
zero ppm frequency accuracy on all
outputs
Flexible input reference:
External crystal: 8 to 30 MHz

CMOS input: 5 to 200 MHz

SSTL/HSTL input: 5 to 350 MHz

Differential input: 5 to 710 MHz

Independently configurable outputs
support any frequency or format:
LVPECL/LVDS: 0.16 to 710 MHz

HCSL: 0.16 to 250 MHz

CMOS: 0.16 to 200 MHz

SSTL/HSTL: 0.16 to 350 MHz

Independent output voltage per driver:
1.5, 1.8, 2.5, or 3.3 V
Applications
Ethernet switch/router
PCI Express 2.0/3.0
Broadcast video/audio timing
Processor and FPGA clocking
Description
The Si5338 is a high-performance, low-jitter clock generator capable of
synthesizing any frequency on each of the device's four output drivers. This timing
IC is capable of replacing up to four different frequency crystal oscillators or
operating as a frequency translator. Using its patented MultiSynth™ technology,
the Si5338 allows generation of four independent clocks with 0 ppm precision.
Each output clock is independently configurable to support various signal formats
and supply voltages. The Si5338 provides low-jitter frequency synthesis in a
space-saving 4 x 4 mm QFN package. The device is programmable via an I
SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or
2
3.3 V core supply. I
C device programming is made easy with the ClockBuilder™
Desktop software available at www.silabs.com/ClockBuilder.
Rev. 1.2 8/12
A
- F
NY
G
ENERATOR
Single supply core with excellent
PSRR: 1.8, 2.5, 3.3 V
Independent frequency increment/
decrement feature enables
glitchless frequency adjustments in
1 ppm steps
Independent phase adjustment on
each of the output drivers with an
accuracy of <20 ps steps
Highly configurable spread
spectrum (SSC) on any output:
Any frequency from 5 to 350 MHz

Any spread from 0.5 to 5.0%

Any modulation rate from 33 to

63 kHz
External feedback mode allows
zero-delay mode
Loss of lock and loss of signal
alarms
2
I
C/SMBus compatible interface
Easy to use programming software
Small size: 4 x 4 mm, 24-QFN
Low power: 45 mA core supply typ
Wide temperature range: –40 to
+85 °C
Any-frequency clock conversion
MSAN/DSLAM/PON
Fibre Channel, SAN
Telecom line cards
1 GbE and 10 GbE
Copyright © 2012 by Silicon Laboratories
, A
R E Q U E N C Y
IN1
IN2
IN3
IN4
IN5
IN6
2
C/
Si5338
- O
NY
UTPUT
Ordering Information:
See page 41.
Pin Assignments
Top View
24
23
22
21
20
19
1
18
17
2
3
16
GND
GND
Pad
4
15
5
14
6
13
7
8
9
10
11
12
CLK1A
CLK1B
VDDO1
VDDO2
CLK2A
CLK2B
Si5338

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Summary of Contents for Silicon Laboratories I2C

  • Page 1 SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or 3.3 V core supply. I C device programming is made easy with the ClockBuilder™ Desktop software available at www.silabs.com/ClockBuilder. Rev. 1.2 8/12 Copyright © 2012 by Silicon Laboratories Si5338...
  • Page 2 Si5338 Functional Block Diagram Output Synthesis Synthesis noclk Stage Stage 1 Stage 2 VDDO0 (PLL) P1DIV_IN MultiSynth CLK0A ÷ ÷P1 ÷M0 CLK0B VDDO1 Loop Phase Filter MultiSynth CLK1A Frequency ÷ ÷M1 Detector P2DIV_IN CLK1B ÷P2 VDDO2 noclk CLK2A MultiSynth ÷ ÷M2 CLK2B MultiSynth...
  • Page 3: Table Of Contents

    Si5338 ABLE O F ONTENTS Section Page 1. Electrical Specifications ...........4 2.
  • Page 4: Electrical Specifications

    Si5338 1. Electrical Specifications Table 1. Recommended Operating Conditions = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Test Condition Unit Ambient Temperature –40 °C 2.97 3.63 Core Supply Voltage 2.25 2.75 1.71...
  • Page 5 Si5338 Table 3. DC Characteristics = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Test Condition Unit 100 MHz on all outputs, — Core Supply Current 25 MHz refclk Core Supply Current 50 MHz refclk —...
  • Page 6 Si5338 Table 5. Performance Characteristics = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Test Condition Unit PLL Acquisition Time — — PLL Tracking Range 5000 20000 — TRACK PLL Loop Bandwidth —...
  • Page 7 Si5338 Table 5. Performance Characteristics (Continued) = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Test Condition Unit Phase Increment/Decrement Pin control — Periods UPDATE Update Time MultiSynth output <18 MHz Number of periods of MultiSynth output frequency Frequency Increment/...
  • Page 8 Si5338 Table 6. Input and Output Clock Characteristics = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Test Condition Units Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6) Frequency —...
  • Page 9 Si5338 Table 6. Input and Output Clock Characteristics (Continued) = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Test Condition Units LVPECL Output common mode — – — Voltage 1.45 V peak-to-peak sin-...
  • Page 10 Si5338 Table 6. Input and Output Clock Characteristics (Continued) = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Test Condition Units  CMOS Output — — Resistance  SSTL Output —...
  • Page 11 Si5338 Table 7. Control Pins = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Condition Unit Input Control Pins (IN3, IN4) –0.1 — 0.3 x V Input Voltage Low 0.7 x V —...
  • Page 12 Si5338 Table 10. Crystal Specifications for 19 to 26 MHz Parameter Symbol Unit Crystal Frequency XTAL (supported)* Load Capacitance (on-chip differential) (recommended) Crystal Output Capacitance  Equivalent Series Resistance Crystal Max Drive Level µW *Note: See "AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices" for how to adjust the registers to accommodate a 12 pF crystal C Table 11.
  • Page 13 Si5338 1,2,3 Table 12. Jitter Specifications = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Test Condition Unit GbE Random Jitter CLKIN = 25 MHz — ps RMS (12 kHz–20 MHz) All CLKn at 125 MHz GbE Random Jitter...
  • Page 14 Si5338 1,2,3 Table 12. Jitter Specifications (Continued) = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Test Condition Unit Output MultiSynth — ps pk-pk operated in fractional mode Deterministic Jitter Output MultiSynth —...
  • Page 15 Si5338 Table 14. Typical Phase Noise Performance Offset Frequency 25 MHz XTAL 27 MHz Ref In 19.44 MHz Ref In Units to 156.25 MHz to 148.3517 MHz to 155.52 MHz 100 Hz –90 –87 –110 dBc/Hz 1 kHz –120 –117 –116 dBc/Hz 10 kHz...
  • Page 16: Typical Application Circuits

    Si5338 2. Typical Application Circuits +3.3 V SD/HD/3G-SDI Video/Audio 0.1 uF Power Supply Decoupling Capacitors Format Converter (1 per VDD or VDDOx pin) 16 15 11 SD/HD/3G SD/HD/3G SDI OUT SDI IN Video Optional XTAL for 27 MHz Deserializer Processor Serializer Free-run Applications XTAL...
  • Page 17: Functional Description

    Si5338 3. Functional Description Output Input Synthesis Synthesis Stage Stage 1 Stage Stage 2 VDDO0 (PLL) MultiSynth CLK0A ÷ ÷M0 CLKIN CLK0B ÷P1 VDDO1 Loop Phase Filter MultiSynth CLK1A Frequency ÷ ÷M1 Detector FDBK CLK1B ÷P2 VDDO2 CLK2A MultiSynth ÷ ÷M2 CLK2B MultiSynth...
  • Page 18: Input Stage

    Si5338 3.2. Input Stage IN3 and IN4 accept single-ended signals from 5 MHz to 200 MHz. The single-ended inputs are internally ac- The input stage supports four inputs. Two are used as coupled; so, they can accept a wide variety of signals the clock inputs to the synthesis stage, and the other without requiring a specific dc level.
  • Page 19 Si5338 Synthesis of the output clocks is performed in two The second stage of synthesis consists of the output stages, as shown in Figure 5. The first stage consists of MultiSynth dividers (MS ). Based on a fractional N a high-frequency analog phase-locked loop (PLL) that divider, the MultiSynth divider shown in Figure 6 multiplies the input stage to a frequency within the switches seamlessly between the two closest integer...
  • Page 20: Output Stage

    Si5338 3.4. Output Stage Each of the outputs can also be enabled or disabled through the I C port. A single pin to enable/disable all The output stage consists of output selectors, output outputs is available in the Si5338K/L/M. dividers, and programmable output drivers as shown in 3.5.
  • Page 21 Si5338 3.5.1. Ordering a Custom NVM Configuration 3.5.2. Creating a New Configuration for RAM The Si5338 is orderable with a factory-programmed Any Si5338 device can be configured by writing to custom NVM configuration. This is the simplest way of registers in RAM through the I C interface.
  • Page 22 Si5338 Disable Outputs Set OEB_ALL = 1; reg230[4] Pause LOL Set DIS_LOL = 1; reg241[7] Write new configuration to device Register accounting for the write-allowed mask (See Si5338 Reference Manual) Use ClockBuilder Desktop v3.0 or later Validate input clock status Input clocks are validated with the LOS alarms.
  • Page 23: Status Indicators

    Si5338 3.5.4. Writing a Custom Configuration to NVM Control & Memory An alternative to ordering an Si5338 with a custom NVM configuration is to use the field programming kit (Si5338/56-PROG-EVB) to write directly to the NVM of Control (OTP) a “blank” Si5338. Since NVM is an OTP memory, it can only be written once.
  • Page 24: Power Consumption

    Si5338 SSTL, it is required to have load circuitry as shown in “AN408: Termination Options for Any-Frequency, Any- Output Clock Generators and Clock Buffers”. The Si5338 EVB has layout pads that can be used for this purpose. When testing for output driver current with 0 = enable LVPECL the same layout pads can be used to Bits reserved...
  • Page 25 Si5338 4 Active Outputs, Fractional Output MS 4 Active Outputs, Integer Output MS 3 Active Outputs, Fractional Output MS 3 Active Outputs, Integer Output MS 2 Active Outputs, Fractional Output MS 2 Active Outputs, Integer Output MS 1 Active Output, Fractional Output MS 1 Active Output, Integer Output MS Output Frequency (MHz) Figure 14.
  • Page 26: Reset Options

    Si5338 3.9. Reset Options management, etc.) or in applications where frequency margining (e.g., f ±5%) is necessary for design There are two types of resets on the Si5338, POR and verification manufacturing test. Frequency soft reset. A POR reset automatically occurs whenever increment or decrement can be applied as fast as the supply voltage on the VDD is applied.
  • Page 27 Si5338 3.10.4. Output Synchronization Upon power up or a soft_reset the Si5338 synchronizes Si5338 the output clocks. With normal output polarity (no output clock inversion), the Si5338 synchronizes the output Clk0 clocks to the falling, not rising edge. Synchronization at the rising edge can be done by inverting all the clocks Clk1 Input...
  • Page 28: Applications Of The Si5338

    Si5338 4. Applications of the Si5338 Because of its flexible architecture, the Si5338 can be +/- 0% configured to serve several functions in the timing path. +/- 1% following sections describe some common +/- 2.5% +/- 5% applications. 4.1. Free-Running Clock Generator Using the internal oscillator (Osc) and an inexpensive external crystal (XTAL), the Si5338 can be configured as a free-running clock generator for replacing high-end...
  • Page 29: Synchronous Frequency Translation

    Si5338 4.2. Synchronous Frequency Translation 4.3. Configurable Buffer and Level Translator In other cases, it is useful to generate an output frequency that is synchronous (or phase-locked) to Using the output selectors, the synthesis stage can be another clock frequency. The Si5338 is the ideal choice entirely bypassed allowing the Si5338 to act as a for generating up to four clocks with different configurable clock buffer/divider with level translation...
  • Page 30: I 2 C Interface

    Si5338 5. I C Interface Write Operation – Single Byte Configuration and operation of the Si5338 is controlled Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] by reading and writing to the RAM space using the I interface.
  • Page 31: Si5338 Registers

    Si5338 6. Si5338 Registers For many applications, the Si5338's register values are easily configured using ClockBuilder Desktop (see "3.1.1. ClockBuilder™ Desktop Software" on page 17). However, for customers interested in using the Si5338 in operating modes beyond the capabilities available with ClockBuilder™, refer to the Si5338 Reference Manual: Configuring the Si5338 without ClockBuilder Desktop for a detailed description of the Si5338...
  • Page 32: Pin Descriptions

    Si5338 7. Pin Descriptions Top View CLK1A CLK1B VDDO1 VDDO2 CLK2A CLK2B Note: Center pad must be tied to GND for normal operation. Table 16. Si5338 Pin Descriptions Pin # Pin Name Signal Type Description CLKIN/CLKINB. These pins are used as the main differential clock input or as the XTAL input.
  • Page 33 Si5338 Table 16. Si5338 Pin Descriptions (Continued) Pin # Pin Name Signal Type Description This pin can have one of the following functions depending on the part number: CLKIN (for Si5338A/B/C and Si5338N/P/Q devices only) Provides a high-impedance clock input for single ended clock signals.
  • Page 34 Si5338 Table 16. Si5338 Pin Descriptions (Continued) Pin # Pin Name Signal Type Description FDBK/FDBKB. These pins can be used as a differential feedback input in zero delay mode or as a secondary clock input. See section 3.2, Figure 3, for termination details. See "3.10.6. Zero-Delay Mode" on IN5/IN6 Multi page 27 for zero delay mode set-up.
  • Page 35 Si5338 Table 16. Si5338 Pin Descriptions (Continued) Pin # Pin Name Signal Type Description Output Clock Supply Voltage. Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK2A,B. VDDO2 Supply A 0.1 µF capacitor must be located very close to this pin. If CLK2 is not used, this pin must be tied to VDD (pin 7, 24).
  • Page 36: Device Pinout By Part Number

    Si5338 8. Device Pinout by Part Number The Si5338 is orderable in three different speed grades: Si5338A/D/G/K/N have a maximum output clock frequency limit of 710 MHz. Si5338B/E/H/L/P have a maximum output clock frequency of 350 MHz. Si5338C/F/J/ M/Q have a maximum output clock frequency of 200 MHz. Devices are also orderable according to the pin control functions available on Pins 3 and 4: ...
  • Page 37 Si5338 Table 17. Pin Function by Part Number (Continued) Pin # Si5338A: 710 MHz Si5338D: 710 MHz Si5338G: 710 MHz Si5338K: 710 MHz Si5338N: 710 MHz Si5338B: 350 MHz Si5338E: 350 MHz Si5338H: 350 MHz Si5338L: 350 MHz Si5338P: 350 MHz Si5338C: 200 MHz Si5338F: 200 MHz Si5338J: 200 MHz...
  • Page 38: Package Outline: 24-Lead Qfn

    Si5338 9. Package Outline: 24-Lead QFN Figure 25. 24-Lead Quad Flat No-lead (QFN) Table 18. Package Dimensions Dimension 0.80 0.85 0.90 0.00 0.02 0.05 0.18 0.25 0.30 4.00 BSC. 2.35 2.50 2.65 0.50 BSC. 4.00 BSC. 2.35 2.50 2.65 0.30 0.40 0.50 0.10...
  • Page 39: Recommended Pcb Land Pattern

    Si5338 10. Recommended PCB Land Pattern Table 19. PCB Land Pattern Dimension 2.50 2.55 2.60 2.50 2.55 2.60 0.20 0.25 0.30 0.75 0.80 0.85 3.90 3.90 0.50 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2.
  • Page 40: Top Marking

    Si5338 11. Top Marking 11.1. Si5338 Top Marking Si5338 Xxxxxx RTTTTT YYWW 11.2. Top Marking Explanation Table 20. Top Marking Explanation Line Characters Description Line 1 Si5338 Base part number. X = Frequency and configuration code. xxxxx = Optional NVM code for custom factory-programmed devices Line 2 Xxxxxx (characters are not included for blank devices).
  • Page 41: Ordering Information

    Si5338 12. Ordering Information Si5338X AXXXXX Operating Temp Range: -40 to +85 °C Package: 4 x 4 mm QFN, ROHS6, Pb-free R = Tape & Reel (ordering option) When ordering non Tape & Reel shipment media, contact your sales representative for more information.
  • Page 42: Errata

    Si5338 13. Errata 13.1. Description: Spread Modulation Rate and Nominal Frequency Error Reset events (e.g., a soft reset or a power cycle) may cause an output clock's nominal frequency and spread modulation rate to be incorrect for Si5338 devices that have output clocks that are configured to enable the spread spectrum feature with “down spread”...
  • Page 43: Document Change List

    Revision 0.6 to 0.65  Deleted Table 12, “Output Driver Slew Rate Control”.  Updated Figure 9, “I2C Programming Procedure,” on Revision 0.3 to 0.5 page 22 for consistency with register description.  Major editorial changes to all sections to improve Revision 0.65 to 1.0...
  • Page 44 Si5338 and 3.0 Data clocked topology.  Added Table 13, “itter Specifications, Clock Buffer Mode (PLL Bypass)*,” on page 14. Updated typical additive jitter (12 kHz–20 MHz) from  0.150 to 0.165 ps RMS.  Updated Figure 9 on page 22 to provide work- around for spread spectrum errata.
  • Page 45 Si5338 OTES Rev. 1.2...
  • Page 46: Contact Information

    Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur.

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