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Pin No.
16
17, 64
18, 63
19
20
21
22
23
24
25 to 29
30
31, 34, 36, 39, 44, 47, 48
32, 33
35, 40, 43
37, 38
41
42
45
46
49
50
51
52
53
54
55
56
57
58
59
60
61
62
1
HD = half-duplex mode; FD = full-duplex mode.
Mnemonic
Mode
RXCLK
HD
FD
DRVDD
DRVSS
CLKOUT1
SDIO
SDO
SCLK
SEN
GAIN
FD
PGA[5]
HD or FD
PGA[4 to 0]
HD or FD
RESET
AVSS
REFB, REFT
AVDD
RX−, RX+
REFADJ
REFIO
IOUT_G−
IOUT_N−
IOUT_G+
IOUT_N+
IOUT_P−
IOUT_P+
MODE
CONFIG
CLKVSS
XTAL
OSCIN
CLKVDD
DVSS
DVDD
CLKOUT2
PWR_DWN
1
Description
ADIO Request Clock Input
Rx and Tx Clock Output at 2 × f
Digital Output Driver Supply Input
Digital Output Driver Supply Return
f
/N Clock Output (L = 1, 2, 4, or 8)
DAC
Serial Port Data Input/Output
Serial Port Data Output
Serial Port Clock Input
Serial Port Enable Input
Tx Data Port (Tx[5:0]) Mode Select
MSB of PGA Input Data Port
Bits 4 to 0 of PGA Input Data Port
Reset Input (Active Low)
Analog Ground
ADC Reference Decoupling Nodes
Analog Power Supply Input
Receive Path − and + Analog Inputs
TxDAC Full-Scale Current Adjust
TxDAC Reference Input/Output
−Tx Amp Current Output_Sink
−Tx Mirror Current Output_Sink
+Tx Amp Current Output_Sink
+Tx Mirror Current Output_Sink
−TxDAC Current Output_Source
+TxDAC Current Output_Source
Digital Interface Mode Select Input
LOW = HD, HIGH = FD
Power-Up SPI Register Default Setting Input
Clock Oscillator/Synthesizer Supply Return
Crystal Oscillator Inverter Output
Crystal Oscillator Inverter Input
Clock Oscillator/Synthesizer Supply
Digital Supply Return
Digital Supply Input
f
/L Clock Output, (L = 1, 2, or 4)
OSCIN
Power-Down Input
Rev. A | Page 11 of 48
AD9866
ADC
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