Gate Driver Circuit: High-Voltage Side - Broadcom ACPL-355JC Reference Manual

62-mm sic module eb1200m62-355jc evaluation board

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ACPL-355JC Reference Manual

UVLO and FAULT signals are open drain, so they are pulled up with 10-kΩ resistors and have 330-pF filtering capacitors.

The logic for these signals is inverted, so they are suitable for wired 'OR' applications. In this case, FAULT signals from both

drivers are connected in parallel, and the same is done with UVLO signals, so the user is notified if a FAULT or UVLO has

occurred regardless of which MOSFET it has occurred on. UVLO has the highest fault priority followed by FAULT.

3.2.2 Gate Driver Circuit: High-Voltage Side

The secondary side of the gate drive circuitry, shown in

a soft shutdown in case of fault.

Figure 14: Gate Driver Circuit – High-Voltage Side

Based on FF6MR12KM1, when the gate driver input is set to high, V

MOSFET gate via two 8.06Ω (default value) parallel resistors. When the gate driver input is set to low, the V

becomes active and –5V is supplied to the MOSFET gate via two 8.06Ω (default value) parallel resistors; and when V

is low, –5V is connected to the MOSFET gate. These voltages are referred to the source of the respective MOSFET. The

switching time is determined by the gate charging and discharging process. Smaller gate resistors lead to higher peak gate

current, which subsequently decreases turn-on and turn-off time, reducing switching losses. However, gate resistors that are

too small may introduce voltage spikes and current oscillations on the MOSFET or can overload the gate driver IC. For the

proper selection of the gate resistors, several criteria must be fulfilled.

First is the limit of the gate peak current. MOSFET internal R

gate resistor and the internal minimum turn-on resistance of driver R

given in the ACPL-355JC data sheet.

Broadcom

Figure

14, includes circuits related to OC and UVLO protection and

becomes high and +15.5V is supplied to the

OUTP

must be considered when calculating the ideal value for the

Gint

. The equation for the gate resistor calculation is

VOUTP

62-mm SiC Module EB1200M62-355JC Evaluation Board

ACPL-355JC-62mmSiC-RM100

OUTN

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